Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.

Abstract: Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

Abstract: Disclosed is a synaptic element that uses electro-migration in an interconnect structure, wherein the interconnect structure is optimized to give control of resistivity change following current flow. The synaptic element exhibits resistivity that is a function of the amount (of charge) and direction of current flow, wherein a continuously variable resistance is obtained by controlling the volume of a designed void in the interconnect structure.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract: A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal cell or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.