Abstract: A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Abstract: An apparatus and method for arbitrating requests for access to a shared resource. A buffer, on command from control logic, can selectively couple or decouple two buses. The control logic uses signals from two logic devices, one of which may be a microprocessor, and one of which may be a communications interface, to determine which of the devices is granted access to the shared resource. The control logic can generate an inhibit signal to the microprocessor to stall it while the second logic device is accessing the shared resource. Handshaking is used to control access by the second device to the shared resource.