Patents by Inventor Gregory B. Shinn
Gregory B. Shinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848268Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: July 16, 2021Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Publication number: 20210343642Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 11101212Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: May 28, 2019Date of Patent: August 24, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 10956646Abstract: In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.Type: GrantFiled: October 12, 2017Date of Patent: March 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tae S. Kim, Gregory B. Shinn
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Publication number: 20190295948Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: May 28, 2019Publication date: September 26, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Publication number: 20190221516Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: January 16, 2018Publication date: July 18, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 10354951Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: January 16, 2018Date of Patent: July 16, 2019Assignee: Texas Instruments IncorporatedInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Publication number: 20190114383Abstract: In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.Type: ApplicationFiled: October 12, 2017Publication date: April 18, 2019Inventors: Tae S. KIM, Gregory B. SHINN
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Patent number: 10249621Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.Type: GrantFiled: December 15, 2016Date of Patent: April 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark Robert Visokay, Tae S. Kim, Mahalingam Nandakumar, Eric D. Rullan, Gregory B. Shinn
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Publication number: 20180175023Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.Type: ApplicationFiled: December 15, 2016Publication date: June 21, 2018Inventors: MARK ROBERT VISOKAY, TAE S. KIM, MAHALINGAM NANDAKUMAR, ERIC D. RULLAN, GREGORY B. SHINN
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Patent number: 8093070Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: GrantFiled: February 15, 2007Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Publication number: 20080081380Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: ApplicationFiled: February 15, 2007Publication date: April 3, 2008Inventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 6821791Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.Type: GrantFiled: February 27, 2003Date of Patent: November 23, 2004Assignee: Texas Instruments IncorporatedInventors: Roger J. Stierman, Thomas M. Moore, Gregory B. Shinn
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Publication number: 20040074517Abstract: Methods and compositions are disclosed for chemical mechanical polishing (CMP) of semiconductor substrates, post-CMP storage of semiconductor substrates and post-CMP cleaning of semiconductor substrates. The methods and compositions feature the use of surfactants and, in some cases, passivation agents. The methods and compositions are particularly suited to polishing, storing and cleaning semiconductor substrates comprising hydrophobic surfaces.Type: ApplicationFiled: October 22, 2002Publication date: April 22, 2004Applicant: Texas Instruments IncorporatedInventors: Vincent C. Korthuis, Mona M. Eissa, Gregory B. Shinn
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Publication number: 20040074518Abstract: Methods and compositions are disclosed for chemical mechanical polishing (CMP) of semiconductor substrates, post-CMP storage of semiconductor substrates and post-CMP cleaning of semiconductor substrates. The methods and compositions feature the use of surfactants and, in some cases, passivation agents. The methods and compositions are particularly suited to polishing, storing and cleaning semiconductor substrates comprising hydrophobic surfaces.Type: ApplicationFiled: October 22, 2002Publication date: April 22, 2004Applicant: Texas Instruments IncorporatedInventors: Vincent C. Korthuis, Mona M. Eissa, Gregory B. Shinn
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Patent number: 6686283Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.Type: GrantFiled: February 4, 2000Date of Patent: February 3, 2004Assignee: Texas Instruments IncorporatedInventors: Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan, Janice D. Makos, Arun Sivasothy, Troy A. Yocum, Jaideep Mavoori, Wayne A. Bather, Joe G. Tran, Ju-Ai Ruan, Michelle L. Hartsell, Gregory B. Shinn
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Publication number: 20030153107Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.Type: ApplicationFiled: February 27, 2003Publication date: August 14, 2003Inventors: Roger J. Stierman, Thomas M. Moore, Gregory B. Shinn
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Patent number: 6534327Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.Type: GrantFiled: April 11, 2001Date of Patent: March 18, 2003Assignee: Texas Instruments IncorporatedInventors: Roger J. Stierman, Thomas M. Moore, Gregory B. Shinn
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Publication number: 20010046721Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.Type: ApplicationFiled: April 11, 2001Publication date: November 29, 2001Inventors: Roger J. Stierman, Thomas M. Moore, Gregory B. Shinn
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Patent number: 6268297Abstract: A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.Type: GrantFiled: November 20, 1998Date of Patent: July 31, 2001Assignee: Texas Instruments IncorporatedInventors: Somnath S. Nag, Gregory B. Shinn, Girish A. Dixit