Patents by Inventor Gregory Djaja
Gregory Djaja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9143164Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.Type: GrantFiled: August 15, 2013Date of Patent: September 22, 2015Assignee: BROADCOM CORPORATIONInventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith
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Patent number: 8723548Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.Type: GrantFiled: May 23, 2012Date of Patent: May 13, 2014Assignee: Broadcom CorporationInventors: Karthik Chandrasekharan, Balaji Narasimham, Gregory Djaja
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Publication number: 20130328704Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Broadcom CorporationInventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith
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Publication number: 20130234753Abstract: A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.Type: ApplicationFiled: May 23, 2012Publication date: September 12, 2013Applicant: BROADCOM CORPORATIONInventors: Karthik Chandrasekharan, Balaji Narasimham, Gregory Djaja
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Patent number: 8514108Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.Type: GrantFiled: May 25, 2011Date of Patent: August 20, 2013Assignee: Broadcom CorporationInventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith
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Publication number: 20120299756Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: BROADCOM CORPORATIONInventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith
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Patent number: 8085076Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.Type: GrantFiled: July 3, 2008Date of Patent: December 27, 2011Assignee: Broadcom CorporationInventors: Gregory Djaja, Karthik Chandrasekharan
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Patent number: 8076965Abstract: A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.Type: GrantFiled: April 10, 2008Date of Patent: December 13, 2011Assignee: Broadcom CorporationInventors: Gregory Djaja, Mark Slamowitz, Karthik Chandrasekharan
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Publication number: 20100001774Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.Type: ApplicationFiled: July 3, 2008Publication date: January 7, 2010Applicant: BROADCOM CORPORATIONInventors: Gregory Djaja, Karthik Chandrasekharan
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Publication number: 20090256608Abstract: A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Applicant: BROADCOM CORPORATIONInventors: Gregory Djaja, Mark Slamowitz, Karthik Chandrasekharan
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Patent number: 6903996Abstract: The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port, where the read port is coupled to the storage element in an isolated manner. The sensing device is adapted to sense a small voltage swing. The sensing device includes two inverters comprising input offset and gain stages.Type: GrantFiled: January 10, 2003Date of Patent: June 7, 2005Assignee: Broadcom CorporationInventors: Mark Slamowitz, Douglas D. Smith, David W. Knebelsberger, Gregory Djaja
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Publication number: 20030099148Abstract: The present invention relates to a multi-port register file memory including a plurality of storage elements in columns. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.Type: ApplicationFiled: January 10, 2003Publication date: May 29, 2003Inventors: Mark Slamowitz, Douglas D. Smith, David W. Knebelsberger, Gregory Djaja
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Patent number: 6519204Abstract: Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.Type: GrantFiled: September 27, 2001Date of Patent: February 11, 2003Assignee: Broadcom CorporationInventors: Mark Slamowitz, Douglas D. Smith, David W. Knebelsberger, Gregory Djaja
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Publication number: 20020071333Abstract: The present invention relates to a multi-port register file memory including a plurality of storage elements in columns. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.Type: ApplicationFiled: September 27, 2001Publication date: June 13, 2002Inventors: Mark Slamowitz, Douglas D. Smith, David W. Knebelsberger, Gregory Djaja
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Patent number: 6405160Abstract: A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user's requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.Type: GrantFiled: August 3, 1998Date of Patent: June 11, 2002Assignee: Motorola, Inc.Inventors: Gregory Djaja, James W. Nicholes, Douglas D. Smith, David William Knebelsberger, Gary Wayne Hancock
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Patent number: 5381055Abstract: A CMOS driver (10) with output feedback pre-drive has been provided. The CMOS driver includes first (14) and second (16) output devices for providing drive current at an output (18). The CMOS driver includes an output feedback pre-drive circuit (12) which includes complementary P and N feedback devices (26, 28, 30, 32) that are coupled across the gate and drain electrodes of the output devices and which are controlled by an input signal.Type: GrantFiled: July 29, 1993Date of Patent: January 10, 1995Assignee: Motorola, Inc.Inventors: Stephen W. Lai, Gregory Djaja, Solomon G. Meskel
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Patent number: 5359535Abstract: A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to more accurately predict the delay time (48). Summing the delay time (48) due to each logic gate (12) which comprises the signal path. Repeating the method for each signal path within the digital circuit until all signal paths are computed. Modifying the digital circuit based on the calculated delay times (48) so as to better satisfy a predetermined measurement criteria.Type: GrantFiled: May 4, 1992Date of Patent: October 25, 1994Assignee: Motorola, Inc.Inventors: Gregory Djaja, Timothy J. Jennings, Douglas W. Schucker, Frederic B. Shapiro