Patents by Inventor Gregory F. Grohoski
Gregory F. Grohoski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762665Abstract: A system includes a multidimensional array of homogenous Functional Configurable Units (FCUs), coupled using a multidimensional array of switches, and a parameter store on the device which stores parameters that tag a subarray of FCUs as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged subarray, by changing the routing through the array of switches. As a result, a multidimensional array of FCUs having unusable elements can still be used.Type: GrantFiled: May 5, 2022Date of Patent: September 19, 2023Assignee: SambaNova Systems, Inc.Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
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Patent number: 11740911Abstract: A system includes a multidimensional array of homogenous Functional Configurable Units (FCUs), coupled using a multidimensional array of switches, and a parameter store on the device which stores parameters that tag a subarray of FCUs as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged subarray, by changing the routing through the array of switches. As a result, a multidimensional array of FCUs having unusable elements can still be used.Type: GrantFiled: May 6, 2022Date of Patent: August 29, 2023Assignee: SambaNova Systems, Inc.Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
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Patent number: 11561803Abstract: A system and method for editing a configuration of a graph executable on a set of configurable assets of a reconfigurable data processor is disclosed. The configurable assets can include processing elements having locations on an integrated circuit and links among the processing elements. The system includes logic to read at least portions of a configuration file in memory. The configuration file can include a topology that maps functions of the graph to the plurality of processing elements and links. The system includes logic to display a graphical interface including graphical objects representing functions mapped to corresponding processing elements and links in a selected portion of the topology. The system includes logic to detect user input identifying a graphical object representing a function mapped to a corresponding processing element or link. The system includes logic to change the topology including mapping of corresponding function.Type: GrantFiled: July 8, 2021Date of Patent: January 24, 2023Assignee: SambaNova Systems, Inc.Inventors: Jibin Zou, Gregory F. Grohoski
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Publication number: 20230016892Abstract: A system includes a multidimensional array of homogenous Functional Configurable Units (FCUs), coupled using a multidimensional array of switches, and a parameter store on the device which stores parameters that tag a subarray of FCUs as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged subarray, by changing the routing through the array of switches. As a result, a multidimensional array of FCUs having unusable elements can still be used.Type: ApplicationFiled: May 6, 2022Publication date: January 19, 2023Applicant: SambaNova Systems, Inc.Inventors: Gregory F. GROHOSKI, Manish K. SHAH, Kin Hing LEUNG
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Publication number: 20230014929Abstract: A system includes a multidimensional array of homogenous Functional Configurable Units (FCUs), coupled using a multidimensional array of switches, and a parameter store on the device which stores parameters that tag a subarray of FCUs as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged subarray, by changing the routing through the array of switches. As a result, a multidimensional array of FCUs having unusable elements can still be used.Type: ApplicationFiled: May 5, 2022Publication date: January 19, 2023Applicant: SambaNova Systems, Inc.Inventors: Gregory F. GROHOSKI, Manish K. SHAH, Kin Hing LEUNG
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Patent number: 11556494Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare homogenous subarrays, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Configuration data is distributed using a statically reconfigurable bus system, to implement the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.Type: GrantFiled: July 16, 2021Date of Patent: January 17, 2023Assignee: SambaNova Systems, Inc.Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
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Publication number: 20230011392Abstract: A system and method for editing a configuration of a graph executable on a set of configurable assets of a reconfigurable data processor is disclosed. The configurable assets can include processing elements having locations on an integrated circuit and links among the processing elements. The system includes logic to read at least portions of a configuration file in memory. The configuration file can include a topology that maps functions of the graph to the plurality of processing elements and links. The system includes logic to display a graphical interface including graphical objects representing functions mapped to corresponding processing elements and links in a selected portion of the topology. The system includes logic to detect user input identifying a graphical object representing a function mapped to a corresponding processing element or link. The system includes logic to change the topology including mapping of corresponding function.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: SambaNova Systems, Inc.Inventors: Jibin ZOU, Gregory F. GROHOSKI
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Patent number: 11409540Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.Type: GrantFiled: July 16, 2021Date of Patent: August 9, 2022Assignee: SambaNova Systems, Inc.Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
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Patent number: 11327771Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.Type: GrantFiled: July 16, 2021Date of Patent: May 10, 2022Assignee: SambaNova Systems, Inc.Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
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Patent number: 10108357Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.Type: GrantFiled: May 3, 2016Date of Patent: October 23, 2018Assignee: Oracle International CorporationInventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
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Publication number: 20160246525Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.Type: ApplicationFiled: May 3, 2016Publication date: August 25, 2016Inventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
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Patent number: 9355689Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.Type: GrantFiled: August 20, 2013Date of Patent: May 31, 2016Assignee: Oracle International CorporationInventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
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Patent number: 9317286Abstract: A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.Type: GrantFiled: March 31, 2009Date of Patent: April 19, 2016Assignee: Oracle America, Inc.Inventors: Christopher H. Olson, Gregory F. Grohoski, Lawrence A. Spracklen
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Patent number: 9213551Abstract: Techniques and structures are disclosed relating to predicting return addresses in multithreaded processors. In one embodiment, a processor is disclosed that includes a return address prediction unit. The return address prediction unit is configured to store return addresses for different ones of a plurality of threads executable on the processor. The return address prediction unit is configured to receive a request for a predicted return address for one of the plurality of threads. The first request includes an identification of the requesting thread. The return address prediction unit is configured to provide the predicted return address to the requesting thread. In some embodiments, the return address prediction unit is configured to store the return addresses in a memory that has a plurality of dedicated portions. In some embodiments, the return address prediction unit is configured to store the return addresses in a memory that has dynamically allocable entries.Type: GrantFiled: March 11, 2011Date of Patent: December 15, 2015Assignee: Oracle International CorporationInventors: Manish K. Shah, Gregory F. Grohoski, Zeid H. Samoail
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Patent number: 9122487Abstract: A system and method for balancing instruction loads between multiple execution units are disclosed. One or more execution units may be represented by a slot configured to accept instructions on behalf of the execution unit(s). A decode unit may assign instructions to a particular slot for subsequent scheduling for execution. Slot assignments may be made based on an instruction's type and/or on a history of previous slot assignments. A cumulative slot assignment history may be maintained in a bias counter, the value of which reflects the bias of previous slot assignments. Slot assignments may be determined based on the value of the bias counter, in order to balance the instruction load across all slots, and all execution units. The bias counter may reflect slot assignments made only within a desired historical window. A separate data structure may store data reflecting the actual slot assignments made during the desired historical window.Type: GrantFiled: June 23, 2009Date of Patent: September 1, 2015Assignee: Oracle America, Inc.Inventors: Robert T. Golla, Gregory F. Grohoski
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Publication number: 20150058549Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: Oracle International CorporationInventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
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Patent number: 8904156Abstract: A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information.Type: GrantFiled: October 14, 2009Date of Patent: December 2, 2014Assignee: Oracle America, Inc.Inventors: Manish K. Shah, Gregory F. Grohoski, Robert T. Golla, Jama I. Barreh
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Patent number: 8654970Abstract: A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.Type: GrantFiled: March 31, 2009Date of Patent: February 18, 2014Assignee: Oracle America, Inc.Inventors: Christopher H. Olson, Gregory F. Grohoski, Lawrence A. Spracklen
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Patent number: 8583902Abstract: Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction defined within the ISA. The Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of a general-purpose register file of the processor, where at least one of operands A, B, N spans at least two registers of general-purpose register file. The instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, where P is the product of at least operand A, operand B, and R^?1.Type: GrantFiled: May 7, 2010Date of Patent: November 12, 2013Assignee: Oracle International CorporationInventors: Christopher H. Olson, Gregory F. Grohoski, Lawrence Spracklen, Nils Gura
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Patent number: 8560814Abstract: Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing hardware resources for an appreciable amount of time. One example of a blocking type instruction is a Montgomery multiplication cryptographic instruction. Each thread can operate in a thread-based mode that allows the insertion of stall cycles during the execution of blocking instructions, during which other threads may utilize the previously blocked hardware resources. At times when multiple threads are scheduled to execute blocking instructions, the thread-based mode may be changed to increase throughput for these multiple threads. For example, the mode may be changed to disallow the insertion of stall cycles. Therefore, the time for sequential operation of the blocking instructions corresponding to the multiple threads may be reduced.Type: GrantFiled: May 4, 2010Date of Patent: October 15, 2013Assignee: Oracle International CorporationInventors: Robert T. Golla, Christopher H. Olson, Gregory F. Grohoski