Abstract: Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

Abstract: Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.

Abstract: A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

Abstract: Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Abstract: Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Abstract: Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Abstract: A dynamic processor configuration and power-up programs a processor's fuse block with configuration signals during processor manufacturing. The processor configuration signals include a core voltage identifier and a system bus frequency identifier. When power is applied to the platform, a control signal is used to prevent power-up of the platform's processor related circuitry. While the platform awaits full power-up, the fuse block is powered up. When the fuse block is powered up, the control signal is used to allow the configuration signals to be read from the fuse block. The processor is configured with core voltage and system bus frequency based on the values read from the fuse block. The platform then performs its boot-up sequence.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Abstract: Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Abstract: Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.

Abstract: An input circuit includes a comparator circuit and a multi-reference circuit. The input circuit receives an input signal and generates an output signal as a function of the input signal and a reference signal received from the multi-reference circuit. The comparator circuit detects a crossing of the input signal relative to the reference signal and causes a corresponding transition of the output signal. In response to the transition of the output signal, the multi-reference circuit provides a different reference signal to the comparator circuit. The reference signals provided by the multi-reference circuit are selected to create hysteresis in the operation of the input circuit.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Abstract: Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit.

Abstract: Arrangements having integrated circuit (IC) voltage and thermal resistance designated on a per IC basis.

Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

Abstract: A shared bus multiprocessor system is provided. The system comprises a communications bus, a first processor, a second processor, and a clock. The first processor has a first output buffer that has a first output delay time. The second processor has a second output buffer that has a second output delay time. The second output delay time is less than the first output delay time. Finally, the clock provides a clock signal to the first and second processors, with the clock signal arriving at the second processor before the first processor.

Abstract: An integrated circuit includes circuitry to test input/output (I/O) devices. Test data is provided to a loopback circuit that drives data through the output buffer to the pad, and back onto the integrated circuit through the input buffer. Separate clock signals, with varying phase, are generated for input synchronous elements and output synchronous elements. The phase, and the relative time delay between the separate clocks, changes as an external clock is varied. The external clock is varied to verify the performance parameters of the I/O devices. Each I/O device includes a shift register that can be coupled to the other buffers in a chain, or can be configured to be in a loop.

Abstract: Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test Tsetup and Thold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.