Patents by Inventor Gregory G. Romas

Gregory G. Romas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9660443
    Abstract: Control circuits with energy recycling for envelope elimination and restoration and related methods are disclosed. A control circuit includes a filter module configured to condition an input power signal to provide an output power signal. An energy recapture module is electrically coupled to the filter module and is configured to capture a portion of residual energy from the filter module and return the portion of the residual energy to the input power signal. A control module is electrically coupled to the filter module and the energy recapture module and is configured to control the filter module to provide the output power signal and is further configured to control the energy recapture module to capture and return the portion of the residual energy to the input power signal.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 23, 2017
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory G. Romas, Jr., Thomas E. Byrd, Huan V. Le, Tyrel D. Parks
  • Patent number: 9571086
    Abstract: A bi-directional switch that includes a first terminal, a second terminal, and a plurality of ballast circuits is provided. Each ballast circuit includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a first input connector, a first output connector, a first body, and a first body diode, and a second MOSFET comprising a second input connector, a second output connector, a second body, and a second body diode. Each first input connector is coupled to the first terminal, each second input connector is coupled to the second terminal, and each first output connector is coupled only to the second output connector of the second MOSFET that is in a same ballast circuit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: February 14, 2017
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory G. Romas, Jr., David L. Hoelscher, Jatin N. Mehta
  • Patent number: 9099876
    Abstract: An energy storage cell, or a plurality of energy storage cells assembled into an apparatus, are self-orienting relative to one or more adjacent energy storage cells. The energy storage cells are capable of sensing their polarity orientation of at least one other energy storage cell and self-orienting its own polarity responsive thereto. Thus, a method for self-orienting a subject energy storage cell includes: sensing the polarity of an adjacent energy storage cell; and setting the polarity of the subject energy storage cell responsive to the sensed polarity if the polarities of the adjacent energy storage cell and the subject energy storage cell are incompatible.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: August 4, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory G Romas, Jacob M Stultz, Thomas E Byrd
  • Patent number: 9052069
    Abstract: A system is presented including a tube light mounted in a tube light socket. The tube light includes a printed wiring board, one or more LEDs mounted to the printed wiring board, and one or more sensors mounted to the printed wiring board. The tube light also includes a power supply mounted to the printed wiring board, such that the power supply is connected to the tube light socket to supply a direct current voltage signal to the printed wiring board. A method is also provided for forming the tube light and mounting the tube light into the tube light socket.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 9, 2015
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Gregory G. Romas, Becky Wallace, Jatin N. Mehta, David L. Hoelscher
  • Publication number: 20140233226
    Abstract: A system is presented including a tube light mounted in a tube light socket. The tube light includes a printed wiring board, one or more LEDs mounted to the printed wiring board, and one or more sensors mounted to the printed wiring board. The tube light also includes a power supply mounted to the printed wiring board, such that the power supply is connected to the tube light socket to supply a direct current voltage signal to the printed wiring board. A method is also provided for forming the tube light and mounting the tube light into the tube light socket.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: Lockheed Martin Corporation
    Inventors: Becky Wallace, Gregory G. Romas, Jatin N. Mehta, David L. Hoelscher
  • Patent number: 8129962
    Abstract: Apparatus and methods for reducing output load transients of a low dropout voltage regulator (“LDO”) are disclosed herein. A voltage regulator includes an output driver coupled to a regulator output pin, the output driver provides current to a load external to the regulator. A clamping device is coupled between the output pin and an internal node of the regulator. The clamping device forces a voltage at a control input of the output driver to follow the voltage at the output pin when the output driver is disabled.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Yong Xie, Gregory G. Romas, Jr.
  • Publication number: 20100039082
    Abstract: Apparatus and methods for reducing output load transients of a low dropout voltage regulator (“LDO”) are disclosed herein. A voltage regulator includes an output driver coupled to a regulator output pin, the output driver provides current to a load external to the regulator. A clamping device is coupled between the output pin and an internal node of the regulator. The clamping device forces a voltage at a control input of the output driver to follow the voltage at the output pin when the output driver is disabled.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Xie, Gregory G. Romas, JR.
  • Patent number: 6815801
    Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: November 9, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Gregory G. Romas, Darrel C. Oglesby, Jr., Scott F. Jasper, Philip Najfus, Venkatesh Govindaraju, ChunLiang Yeh, James Lisenby
  • Publication number: 20040169257
    Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Darrel C. Oglesby, Scott F. Jasper, Philip Najfus, Venkatesh Govindaraju, ChunLiang Yeh, James Lisenby
  • Patent number: 6706606
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
  • Publication number: 20040017674
    Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.
    Type: Application
    Filed: June 24, 2003
    Publication date: January 29, 2004
    Inventors: Gregory G. Romas, Rex W. Pirkle
  • Patent number: 6674316
    Abstract: Trimming methods and apparatus are disclosed for selectively removing resistance between first and second nodes in an electrical device, including trim circuits comprising a resistor and a diode formed in the resistor body having a conductive portion which may be selectively melted to short the resistor. A multi-bit trim cell is disclosed having trim cells individually comprising a resistor with a diode formed in the resistor body for selectively shorting the resistor, and a fuse for selectively disconnecting the diode from a trim pad.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: January 6, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Jian Wang
  • Publication number: 20040000700
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Application
    Filed: June 19, 2003
    Publication date: January 1, 2004
    Inventors: Gregory G. Romas, Darrel C. Oglesby
  • Publication number: 20030193361
    Abstract: Trimming methods and apparatus are disclosed for selectively removing resistance between first and second nodes in an electrical device, including trim circuits comprising a resistor and a diode formed in the resistor body having a conductive portion which may be selectively melted to short the resistor. A multi-bit trim cell is disclosed having trim cells individually comprising a resistor with a diode formed in the resistor body for selectively shorting the resistor, and a fuse for selectively disconnecting the diode from a trim pad.
    Type: Application
    Filed: April 12, 2002
    Publication date: October 16, 2003
    Inventors: Gregory G. Romas, Jian Wang
  • Patent number: 6605859
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 12, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
  • Patent number: 6597013
    Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: July 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Rex W. Pirkle
  • Patent number: 6586985
    Abstract: An electrical device is disclosed, comprising electrical components forming an electrical circuit, with a trim circuit comprising two or more trim cells providing selectively removable resistances between first and second nodes in the electrical circuit. The resistance between the nodes is trimmed incrementally by application of trim signals to a single pair of terminals or pads on the device, allowing post-packaging trimming. Methods are also disclosed for selective removal of resistance between first and second nodes in a packaged electrical device.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: July 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Jian Wang
  • Publication number: 20030025178
    Abstract: A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.
    Type: Application
    Filed: August 6, 2001
    Publication date: February 6, 2003
    Inventors: Gregory G. Romas, Rex W. Pirkle