Patents by Inventor Gregory Henry
Gregory Henry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967001Abstract: Systems and methods for generating a video of a user-defined virtual reality scene are disclosed. Exemplary implementations may: obtain a scene definition; obtain camera information for multiple virtual cameras to be used in generating a two-dimensional presentation of the virtual reality scene; execute a simulation of the virtual reality scene from the scene definition for at least a portion of the scene duration; obtain camera timing instructions specifying which of the virtual cameras should be used to generate the two-dimensional presentation of the virtual reality scene as a function of progress through the scene duration; generate the two-dimensional presentation of the virtual reality scene in accordance with the camera timing instructions and the camera information.Type: GrantFiled: April 13, 2023Date of Patent: April 23, 2024Assignee: Mindshow Inc.Inventors: Gil Baron, Daniel Andrew Bellezza, Jeffrey Scott Dixon, William Stuart Farquhar, Jason Zesheng Hwang, John Henry Kanikula Peters, Nhan Van Khong, Christopher Robert Laubach, Gregory Scott Pease, Jonathan Michael Ross
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Publication number: 20240111825Abstract: An apparatus to facilitate single precision support for systolic pipeline in a graphics environment is disclosed. The apparatus includes a processor comprising systolic array hardware including a plurality of data processing units, wherein the systolic array hardware is to: receive data for performance of a matrix multiplication operation in a first precision format; convert an original value of the data into two split values with a second precision format having a lower precision than the first precision format; perform the matrix multiplication operation using the two split values in the second precision format, the matrix multiplication operation comprising a split-term operation that utilizes two passes through the systolic array hardware with feedback wiring and local reduction; and generate an emulated result for the matrix multiplication operation in the first precision format.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jiasheng Chen, Changwon Rhee, Kevin Hurd, Gregory Henry, Peter Caday, Kristopher Wong
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Publication number: 20240111826Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jiasheng Chen, Kevin Hurd, Changwon Rhee, Jorge Parra, Fangwen Fu, Theo Drane, William Zorn, Peter Caday, Gregory Henry, Guei-Yuan Lueh, Farzad Chehrazi, Amit Karande, Turbo Majumder, Xinmin Tian, Milind Girkar, Hong Jiang
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Publication number: 20240065836Abstract: Components for valve treatment systems are disclosed. Valve treatment systems can include a delivery system for an implantable device. The delivery system can include one or more of clasp control components slidably disposed on a catheter handle, a control element for opening and closing the implantable device, a catheter assembly with features to reduce friction with another catheter assembly, grips for attaching catheter assemblies to clamps, catheter assemblies with features that stiffen or provide variable stiffness, and catheter assemblies with one or more steering control lumens incorporated into a reinforcement layer.Type: ApplicationFiled: October 27, 2023Publication date: February 29, 2024Inventors: Michael J. Popp, Nicolas Schleiger, Kevin Gantz, George Lee Matlock, Aric Daniel Stone, Eric Robert Dixon, Charles Henry Bloodworth, IV, Gregory Scott Tyler, II, Asher L. Metchik, Robert Bowes, Waina Michelle Chu, Zachary James Zira, Steven Park
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Patent number: 11868770Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: GrantFiled: December 29, 2022Date of Patent: January 9, 2024Assignee: INTEL CORPORATIONInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20230214215Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: ApplicationFiled: December 29, 2022Publication date: July 6, 2023Inventors: Gregory HENRY, Alexander HEINECKE
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Patent number: 11669586Abstract: The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.Type: GrantFiled: February 25, 2022Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20230086275Abstract: Emulating floating point calculation using lower precision format calculations is described. An example of a processor includes a floating point unit (FPU) to provide a native floating point operation in a first precision format; and systolic array hardware including multiple data processing units, wherein the processor is to receive data for performance of a matrix multiplication operation in the first precision format; enable an emulated floating point multiplication operation using one or more values with a second precision format, the second precision format having a lower precision than the first precision format, the emulated floating point multiplication including operation of the systolic array hardware; and generate an emulated result for the matrix multiplication operation.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Jiasheng Chen, Changwon Rhee, Sabareesh Ganapathy, Gregory Henry, Fangwen Fu
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Publication number: 20230008856Abstract: An DNN accelerator can perform fixed-point emulation of floating-point computation. In a multiplication operation on two floating-point matrices, the DNN accelerator determines an extreme exponent for a row in the first floating-point matrix and determines another extreme exponent for a column in the second floating-point matrix. The row and column can be converted to fixed-point vectors based on the extreme exponents. The two fixed-point vectors are fed into a PE array in the DNN accelerator. The PE array performs a multiplication operation on the two fixed-point vectors and generates a fixed-point inner product. The fixed-point inner product can be converted back to a floating-point inner product based on the extreme exponents. The floating-point inner product is an element in the matrix resulted from the multiplication operation on the two floating-point matrices. The matrix can be accumulated with another matrix resulted from a fixed-point emulation of a floating-point matrix multiplication.Type: ApplicationFiled: September 5, 2022Publication date: January 12, 2023Inventors: Gregory Henry, Kermin Chofleming, Simon Steely, JR.
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Patent number: 11544057Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: GrantFiled: October 13, 2020Date of Patent: January 3, 2023Assignee: INTEL CORPORATIONInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20220391470Abstract: The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.Type: ApplicationFiled: February 25, 2022Publication date: December 8, 2022Inventors: Gregory Henry, Alexander Heinecke
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Patent number: 11263291Abstract: The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.Type: GrantFiled: June 26, 2020Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20210406339Abstract: The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Gregory Henry, Alexander Heinecke
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Patent number: 11126428Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: GrantFiled: December 17, 2020Date of Patent: September 21, 2021Assignee: INTEL CORPORATIONInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20210103444Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Inventors: Gregory HENRY, Alexander HEINECKE
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Publication number: 20210089303Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: ApplicationFiled: October 13, 2020Publication date: March 25, 2021Inventors: Gregory HENRY, Alexander HEINECKE
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Patent number: 10958678Abstract: A method includes generating a behavioral state for an endpoint device based on actor identities and corresponding subject identities for a plurality of operations wherein for each operation, a respective actor represented by a respective actor identity performs the operation upon a respective subject represented by a respective subject identity. Performance of a later operation by an actor with an actor identity upon a subject with a subject identity is recorded and the actor identity and the subject identity are used to determine that the performance of the later operation does not match the behavioral state and indicates a security risk.Type: GrantFiled: June 7, 2019Date of Patent: March 23, 2021Assignee: IDFUSION, LLCInventors: Gregory Henry Wettstein, Scott Byron Stofferahn, Richard William Engen, Johannes Christian Grosen
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Patent number: 10853067Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.Type: GrantFiled: September 27, 2018Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Gregory Henry, Alexander Heinecke
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Publication number: 20190312902Abstract: A method includes generating a behavioral state for an endpoint device based on actor identities and corresponding subject identities for a plurality of operations wherein for each operation, a respective actor represented by a respective actor identity performs the operation upon a respective subject represented by a respective subject identity. Performance of a later operation by an actor with an actor identity upon a subject with a subject identity is recorded and the actor identity and the subject identity are used to determine that the performance of the later operation does not match the behavioral state and indicates a security risk.Type: ApplicationFiled: June 7, 2019Publication date: October 10, 2019Inventors: Gregory Henry Wettstein, Scott Byron Stofferahn, Richard William Engen, Johannes Christian Grosen
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Patent number: 10356116Abstract: An Identity Based Behavior Measurement Architecture (such as the BMA) and related technologies are described herein. In an exemplary embodiment, the BMA can be derived from an IMA and use an identity model to express a deterministic measurement value for platform behavior.Type: GrantFiled: April 6, 2017Date of Patent: July 16, 2019Assignee: IDfusion, LLCInventors: Gregory Henry Wettstein, Scott Byron Stofferahn, Richard William Engen, Johannes Christian Grosen