Patents by Inventor Gregory Joseph McKnight

Gregory Joseph McKnight has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140372772
    Abstract: A self-powered processing device comprises both a processing device and a power generator that are physically, electrically, and thermally coupled to one another. The power generator can be a fuel cell that can be manufactured from materials that can also support processing circuitry, such as silicon-based materials. A thermal coupling between the power generator and the processing device can include a thermoelectric either generating electrical power from the temperature differential or consuming electrical power to generate a temperature differential. A computing device with self-powered processing devices also includes energy storage devices to store excess energy produced by the self-powered processing device and provide it back during times of need. The self-powered processing device comprises either a wireless or wired network connection, the latter being connectable to a slot on a backplane that can aggregate multiple self-powered processing devices and provide fuel delivery paths for them.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Gregory Joseph McKnight, Christian L. Belady, Brandon Aaron Rubenstein, Brian Janous, Sean M. James
  • Publication number: 20140195366
    Abstract: A bid-based network sells network capacity on a transaction-by-transaction basis in accordance with bids placed on transactions. A transaction is the transmission of a quantum of data across at least some portion of the network, where the quantum of data can be as small as a single packet. Bids for network capacity are ranked in order of monetary value, or other criteria relevant to the network service provider. The amount charged to the highest bidder is based on the maximum bid of the next highest bidder. Bids are evaluated on a real-time basis at the time when the link is ready to transmit data. An automated system makes individual bids at each link through which data is transmitted and can take into account additional criteria that can be specified as part of the bid information, including latency and routing requirements. Bid information is passed with data through the network.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Gregory Joseph McKnight, David T. Harper, III, Christopher Hanaoka, Eric C. Peterson, Ming Zhang
  • Publication number: 20140173299
    Abstract: Computing devices receive power from multiple fuel cells, consuming natural gas and outputting electrical energy natively consumable by the computing devices. The fuel cells are sized to provide power to a set of computing devices, such as a rack thereof. The computing devices of a failed fuel cell can receive power from adjacent fuel cells. Additionally, the fuel cells and computing devices are positioned to realize thermal symbiotic efficiencies. Controllers instruct the computing devices to deactivate or throttle down power consuming functions during instances where the power consumption demand is increasing faster than the power being sourced by fuel cells, and instruct the computing devices to activate or throttle up power consuming functions during instances where the power consumption demand is decreasing faster than the power being sourced by the fuel cells. Supplemental power sources, supplementing the fuel cells' inability to quickly change power output, are not required.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Gregory Joseph McKnight, Shaun L. Harris, Sean M. James
  • Patent number: 8756440
    Abstract: A computer system comprising a motherboard and a power supply having an associated power management bus controller with memory storing the power capacity of the associated power supply. A power circuit provides power from the power supply to the motherboard, wherein the motherboard has a processor and a baseboard management controller. The system further comprises a power management bus providing communication between the baseboard management controller and the power management bus controller associated with the selected power supply, wherein the power management bus controller provides the stored power capacity to the baseboard management controller. This allows the baseboard management controller to limit operation of the processor to control the amount of power consumed from exceeding the power capacity of the selected power supply. The power capacity of the power supply may be sent to the baseboard management controller in response to booting the motherboard.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Raymond Mathew Clemo, Nickolas John Gruendler, Beth Frayne Loebach, Gregory Joseph McKnight
  • Publication number: 20090265564
    Abstract: A computer system comprising a motherboard and a power supply having an associated power management bus controller with memory storing the power capacity of the associated power supply. A power circuit provides power from the power supply to the motherboard, wherein the motherboard has a processor and a baseboard management controller. The system further comprises a power management bus providing communication between the baseboard management controller and the power management bus controller associated with the selected power supply, wherein the power management bus controller provides the stored power capacity to the baseboard management controller. This allows the baseboard management controller to limit operation of the processor to control the amount of power consumed from exceeding the power capacity of the selected power supply. The power capacity of the power supply may be sent to the baseboard management controller in response to booting the motherboard.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 22, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond Mathew Clemo, Nickolas John Gruendler, Beth Frayne Loebach, Gregory Joseph McKnight
  • Patent number: 7016972
    Abstract: A method and system for providing performance analysis on a computer system is disclosed. The computer system includes at least one resource group and at least one node. The method and system include obtaining performance data for a plurality of monitors for the at least one resource group and analyzing the performance data to determine whether performance of the system can be improved using the at least one resource group. Preferably, performance is improved by moving the resource group between nodes. The method and system include graphically displaying the performance data graphically displaying performance data for at least one monitor of the plurality of monitors for the at least one resource group.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Randal Lee Bertram, Antonio Abbondanzio, Janet Anne Brewer, James Franklin Macon, Jr., Gregory Joseph McKnight, Walter Cade Metz, Jr.
  • Patent number: 6961794
    Abstract: A data processing system and method analyze the performance of its components by obtaining measures of usage of the components over time as well as electrical requirements of those components to recommend an optimal configuration. The location in the system and the time duration that any one or more components is in a performance-limiting or bottleneck condition is determined. Based on the observed bottlenecks, their times of occurrence and their time duration, more optimal configurations of the system are recommended. The present invention is particularly adapted for use in data processing systems where a peripheral component interconnect (PCI) bus is used.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: November 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Edward Atherton, Randal Lee Bertram, Gregory Joseph McKnight, William Joseph Piazza
  • Patent number: 6941450
    Abstract: A system and method for implementing a system optimizer utilized to determine if a current configuration of a data processing system is optimized for system performance according to testing criteria. If the current configuration is not optimized, alternate configurations are generated and analyzed to find at least one optimized alternate configuration. If an optimized alternate configuration is found, the system optimizer notifies a user. However, if at least one optimized alternate configuration is not found, the testing criteria is altered and the set of generated alternate configurations are analyzed utilizing the altered testing criteria.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Edward Atherton, Gregory Joseph McKnight, William Joseph Piazza
  • Patent number: 6629211
    Abstract: A method and system for accessing data in a redundant array of inexpensive disks (RAID) subsystem is disclosed. The RAID subsystem includes a RAID controller having a cache and a plurality of disks. The method and system include utilizing the cache in a write back mode if the RAID subsystem is lightly loaded. In write back mode, the data is written to the cache prior to storing the data on at least one disk of the plurality of disks or prior to outputting the data from the RAID subsystem. The method and system also include utilizing the cache in a write through mode if the RAID subsystem is heavily loaded. In the write through mode, the data is written directly to at least one disk of the plurality of disks and, in a preferred embodiment, at the same time written to any cache buffer. Thus, data is written to the disks without the delay associated with managing a full cache when in write back mode required to flush an existing cache buffer to make a free buffer available.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gregory Joseph McKnight, Linda Ann Riedle, Charles Thorpe Stephan
  • Patent number: 6557035
    Abstract: A method of optimizing server hardware performance and predicting server hardware bottlenecks monitors server hardware utilization parameters over a selected time period and computes the averages of the measurements. The method then compares the computed averages to thresholds. If some of the computed averages are equal to or greater than the threshold, the method reports a performance bottleneck and provides a recommended solution for the bottleneck. The method predicts a future server hardware performance bottleneck by computing running averages of the measured server utilization parameters. The method uses a linear regression analysis to determine a trend in the running averages and compares the trend to threshold values to predict the occurrence of a performance bottleneck.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventor: Gregory Joseph McKnight
  • Publication number: 20030061324
    Abstract: A data processing system and method analyze the performance of its components by obtaining measures of usage of the components over time as well as electrical requirements of those components to recommend an optimal configuration. The location in the system and the time duration that any one or more components is in a performance-limiting or bottleneck condition is determined. Based on the observed bottlenecks, their times of occurrence and their time duration, more optimal configurations of the system are recommended. The present invention is particularly adapted for use in data processing systems where a peripheral component interconnect (PCI) bus is used.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: William Edward Atherton, Randal Lee Bertram, Gregory Joseph McKnight, William Joseph Piazza
  • Publication number: 20030023841
    Abstract: A system and method for implementing a system optimizer utilized to determine if a current configuration of a data processing system is optimized for system performance according to testing criteria. If the current configuration is not optimized, alternate configurations are generated and analyzed to find at least one optimized alternate configuration. If an optimized alternate configuration is found, the system optimizer notifies a user. However, if at least one optimized alternate configuration is not found, the testing criteria is altered and the set of generated alternate configurations are analyzed utilizing the altered testing criteria.
    Type: Application
    Filed: July 30, 2001
    Publication date: January 30, 2003
    Applicant: International Business Machines Corporation
    Inventors: William Edward Atherton, Gregory Joseph McKnight, William Joseph Piazza
  • Publication number: 20030014507
    Abstract: A method and system for providing performance analysis on a system including a cluster is described. The cluster includes a plurality of nodes. The method and system include obtaining data for the plurality of nodes and analyzing the data. The data obtained relates to a plurality of monitors for the plurality of nodes. The analysis is used to determine whether performance of the cluster can be improved. The method and system also include providing at least one remedy to improve performance of the cluster if the performance of the cluster can be improved. The at least one remedy is capable of including a cluster level remedy.
    Type: Application
    Filed: March 13, 2001
    Publication date: January 16, 2003
    Applicant: International Business Machines Corporation
    Inventors: Randal Lee Bertram, Antonio Abbondanzio, Janet Anne Brewer, F.S. Hunter Krauss, James Franklin Macon, Gregory Joseph McKnight
  • Publication number: 20020156884
    Abstract: A method and system for providing performance analysis on a computer system is disclosed. The computer system includes at least one resource group and at least one node. The method and system include obtaining performance data for a plurality of monitors for the at least one resource group and analyzing the performance data to determine whether performance of the system can be improved using the at least one resource group. Preferably, performance is improved by moving the resource group between nodes. The method and system include graphically displaying the performance data graphically displaying performance data for at least one monitor of the plurality of monitors for the at least one resource group.
    Type: Application
    Filed: April 23, 2001
    Publication date: October 24, 2002
    Applicant: International Business Machines Corporation
    Inventors: Randal Lee Bertram, Antonio Abbondanzio, Janet Anne Brewer, James Franklin Macon, Gregory Joseph McKnight, Walter Cade Metz
  • Publication number: 20020156972
    Abstract: A method and system for accessing data in a redundant array of inexpensive disks (RAID) subsystem is disclosed. The RAID subsystem includes a RAID controller having a cache and a plurality of disks. The method and system include utilizing the cache in a write back mode if the RAID subsystem is lightly loaded. In write back mode, the data is written to the cache prior to storing the data on at least one disk of the plurality of disks or prior to outputting the data from the RAID subsystem. The method and system also include utilizing the cache in a write through mode if the RAID subsystem is heavily loaded. In the write through mode, the data is written directly to at least one disk of the plurality of disks and, in a preferred embodiment, at the same time written to any cache buffer. Thus, data is written to the disks without the delay associated with managing a full cache when in write back mode required to flush an existing cache buffer to make a free buffer available.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 24, 2002
    Applicant: International Business Machines Corporation
    Inventors: Gregory Joseph McKnight, Linda Ann Riedle, Charles Thorpe Stephan
  • Patent number: 6434613
    Abstract: A system and method of monitoring and analyzing the performance of a server and its components in a data processing network and for proposing changes to the network to improve the performance. The system involves identifying bottlenecks in the system, determining which bottlenecks are the most severe in affecting the performance of the system and in proposing changes to the components of the system to improve performance of the network. Identification of latent bottlenecks caused by fixing other bottlenecks and creating a more efficient system is a part of the present invention, using a second, lower threshold for identifying latent bottleneck when a realized bottleneck has also been identified in a system.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Randal Lee Bertram, Gregory Joseph McKnight