Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

Abstract: System and techniques for spike timing dependent plasticity (STDP) in neuromorphic hardware are described herein. A first spike may be received, at a first neuron at a first time, from a second neuron. The first neuron may produce a second spike at a second time after the first time. At a third time after the second time, the first neuron may receive a third spike from the second neuron. Here, the third spike is a replay of the first spike with a defined time offset. The first neuron may then perform long term potentiation (LTP) for the first spike using the third spike.

Abstract: Systems and methods may apply homeostatic plasticity control in a spiking neural network, such as at a neuron of a core of the spiking neural network. The neuron may receive input spike information and determine whether to activate an output spike at the neuron based at least in part on the input spike information and a bias value. The bias value may be set based on whether the neuron issued a previous output spike during a previous time period. The bias value may be updated based on whether the output spike was activated at the neuron. For example, in accordance with a determination to activate the output spike, the bias value may be decreased, and in accordance with a determination to not activate the output spike, the bias value may be increased.

Abstract: System and techniques for spike timing dependent plasticity (STDP) in neuromorphic hardware are described herein. A first spike may be received, at a first neuron at a first time, from a second neuron. The first neuron may produce a second spike at a second time after the first time. At a third time after the second time, the first neuron may receive a third spike from the second neuron. Here, the third spike is a replay of the first spike with a defined time offset. The first neuron may then perform long term potentiation (LTP) for the first spike using the third spike.

Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

Abstract: An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12. Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34. The power supply circuitry 10, 12 is then configured to alter the voltage supply to the malfunctioning memory cells 14 in an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.

Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.

Abstract: A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.

Abstract: A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.

Abstract: An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12. Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34. The power supply circuitry 10, 12 is then configured to alter the voltage supply to the malfunctioning memory cells 14 in an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.

Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.