Patents by Inventor Gregory Lemos

Gregory Lemos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8442075
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Publication number: 20110170584
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Patent number: 7936789
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Publication number: 20070230509
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Hing (Thomas) To, Gregory Lemos
  • Publication number: 20070079167
    Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventor: Gregory Lemos