Abstract: The present invention generally provides embodiments relative to a method for PCI interrupt routing in a logically partitioned guest operating system. The method, which may be embodied upon a computer readable medium and executed by a processor, may include the steps of locating primary PCI buses, initializing IRQ tables, locating hardware interrupt sources, and activating an interrupt handling process. Embodiments of the present invention include the capability to mask and unmask function interrupts for each device associated with the guest operating system, wherein the process of masking and unmasking function interrupts may include calling a hypervisor to associate an OS IRQ number with a slot.

Abstract: A method, which may be embodied upon a computer readable medium and executed by a processor, for detecting PCI buses in a logically partitioned system. The method may include determining PCI buses that are accessible to a guest operating system via querying a hypervisor, generating a PCI controller list, wherein a PCI controller exists for each determined PCI bus, and constructing a PCI bus structure for each PCI controller in the PCI controller list. The method may further include calling a platform dependent device detection code to detect PCI devices accessible to the logically partitioned system, and connecting to each function of each detected PCI device to authorize the guest operating system to conduct configuration IO operations thereon through a platform dependent code operation.

Abstract: A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

Abstract: In an electrical interface providing a predefined number of connections at least some of which have predefined functions and at least some of which have reserved, undefined or non-critical functions, selective use of at least one of the connections having a reserved, undefined or non-critical function is accomplished. At least one switch is provided which is controllable and coupled to switch at least one connection having a reserved, undefined or non-critical function to a desired customized function. In this way, the electrical interface can be selectively switched to provide additional functionality using reserved, undefined or non-critical connections of the interface.

Abstract: An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count.

Abstract: An I/O adapter connects an I/O adapter to an I/O bus and includes a device interrupt status register and an interrupt status shadow address register. The device interrupt status register stores the interrupt status of the I/O adapter. The I/O adapter accesses the interrupt status shadow address register to determine an address of main memory at which the device interrupt status register is shadowed. After shadowing the interrupt status, the I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status. A multifunction I/O adapter permits a plurality of I/O adapters to be connected thereto and includes a function interrupt status register to summarize the interrupt status of all the I/O adapters attached thereto. After shadowing the summarized interrupt status, the multifunction I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status.

Abstract: An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state.

Abstract: In an electronic system having at least one enclosure including at least one connecting board with at least one associated device coupled thereto, a respective physical location of each device is electronically determined, and an indication of each respective physical location is stored in memory disposed in the at least one enclosure. An operating system uses the stored physical location indication to correlate logical addresses to physical location.

Abstract: An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

Abstract: An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.