Abstract: The basic concept of the present invention comprises converting a standard buffer circuit into an adjustable buffer circuit that will in effect reduce the operating speed and power consumption of the IC in which it is constructed. An adjustable buffer circuit can be designed into a chip design that will allow manufacturing to either use a bonding option or the blowing of a fuse to adjust its operating speed and active power consumption. One important application would be in memory devices such as for static random access memory (SRAM) devices. For example, if may be desirable to allow a -15 ns access time SRAM to be downgraded to a -20 ns or -35 ns access time device while lowering its active power consumption by .apprxeq.20-30% so that it will pass the -35 ns I.sub.CC specification rating.

Abstract: The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-7000V HBM (the Mil. Std. human body model (HBM) test model) and +/-600V MM EIAJ (the EIAJ machine model (MM) test model) ESD protection response. The series n+ active area resistor is placed inside an n-well as are all metal contacts to the input, to improve junction integrity during an ESD event. The parallel SCR circuit is designed in a layout that has an n+ diffusion area tied to V.sub.SS surrounding the n+/p+ diffusion inside the n-well on three sides to provide greater surface area for current distribution.

Abstract: The invention is a coupling circuit for quickly increasing the differential potential between non-selected bit lines and selected bit lines in the case where the digital data has a high logic state, while retaining a valid differential potential for the case where the digital data has a low logic state. The circuit comprises a true and a complement coupling line typically held at an equilibrate potential substantially equal to the equilibrate potential of the bit lines. A coupling capacitor is electrically interposed between each of the true bit lines and the true coupling line and a coupling capacitor is electrically interposed between each of the complement bit lines and the complement coupling line. During cell selection the potential of the coupling line in electrical communication with the non-selected bit lines is switched to a reference potential by select coupling line circuitry.

Abstract: The basic component of the output ESD protection circuit of the present invention comprises a low resistance connected in series between an output pad and conventional active output pad pullup and pulldown drivers. In a preferred embodiment, a polysilicon resistor is connected in series between an output pad and a metal bus. On the metal bus, a lateral bipolar device is connected in parallel to an n-channel pulldown at an output node and a common potential (conventionally labeled as V.sub.SS). The pullup device is also an active n-channel pullup device connected between an operating potential (conventionally labeled as V.sub.CC) and the output node. Both drains of the two n-channel devices have n-well underneath the n+ diffusion in the area where metal contacts are formed to thereby prevent metal spiking to the substrate during an ESD event. This circuitry combination provides ESD protection equal to or greater than the voltage range of +8000/-2000 V for the HBM response (the Mil. Std.

Abstract: An area-efficient, low-noise transmission line structure for use in integrated circuits, which may be used to carry a high-frequency AC signal from a source location to one or more destination locations. This transmission line structure effectively decouples high-frequency signals carried by a signal line from a subjacent substrate. The structure comprises a dielectric layer subjacent the entire length of the signal line, a well of semiconductor material having a conductivity type opposite to that of the substrate, with the well being positioned beneath the signal line, extending substantially the entire distance between the source location and each destination location, being electrically insulated from the signal line by the dielectric layer, and forming a P-N junction with the substrate. The junction, which is maintained in a reverse-biased state, possesses a parasitic capacitance that is larger than the parasitic capacitance existing between the signal line and the well.

Abstract: A six-transistor latch cell is formed with resistors connecting opposite nodes of the latch. A Salicide (self-aligned silicide) isolation mask layer (25) is used to permit the use of a single layer of polysilicon (23) to implant both the two resistors and the six transistors. The Salicide isolation mask (25) is provided to mask all high energy dopant implants in the poly resistor region and to function as a dielectric between the poly resistor and the local interconnect (27) passing above it. This Salicide isolation layer (25) is easy to manufacture, and adds very little to the vertical topology.

Abstract: A voltage level conversion circuit which may be used on CMOS integrated circuit semiconductor devices uses a regulated power supply to drive an internal array and periphery logic. The voltage converter includes a first inverter (31), an isolating transistor (Q3), and an output inverter (35). An isolating transistor (Q3) admits current to the output inverter (35) until the output inverter (35) switches its output level. An active biasing circuit, including transistor Q4, causes inverter (35) to remain at a low state after the isolating transistor (Q3) gates off, thereby allowing the output inverter to continue to provide its output in isolation from the first inverter's output voltage.