Patents by Inventor Gregory R. McIntyre
Gregory R. McIntyre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7831942Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.Type: GrantFiled: December 12, 2006Date of Patent: November 9, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Patent number: 7818707Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.Type: GrantFiled: December 12, 2006Date of Patent: October 19, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Publication number: 20100208264Abstract: This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a specially designed polarization monitoring reticle for high numerical aperture lithographic scanners. The reticle measures 25 locations across the slit and is designed for numerical apertures above 0.85. The monitors provide a large polarization dependent signal which is more sensitive to polarization. A double exposure method is also provided using two reticles where the first reticle contains the polarization monitors, clear field reference regions and low dose alignment marks. The second reticle contains the standard alignment marks and labels. For a single exposure method, a tri-PSF low dose alignment mark is used. The reticles also provide for electromagnetic bias wherein each edge is biased depending on that edge's etch depth.Type: ApplicationFiled: February 18, 2010Publication date: August 19, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy A. Brunner, Gregory R. McIntyre
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Publication number: 20100178619Abstract: The present invention relates to photolithography methods for enhancing lithographic imaging of isolated and semi-isolated features. A first layer of a first photoresist is formed over a substrate. A second layer of a second photoresist is formed over the first layer. The second photoresist includes a polymer containing an absorbing moiety. The second layer is exposed through a first patterned mask and developed to form a first relief image. The first relief image and the first layer are exposed through a second patterned mask. One of the first and the second patterned masks includes a dense pattern, while the other includes an isolated or a semi-isolated pattern. The first relief image and base soluble regions of the first layer are removed to form a second relief image with an isolated or a semi-isolated pattern. The second layer can also be bleachable upon exposure and bake in the present invention.Type: ApplicationFiled: January 15, 2009Publication date: July 15, 2010Applicant: International Business Machines CorporationInventors: Wu-Song Huang, Gregory R. McIntyre
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Patent number: 7752577Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.Type: GrantFiled: December 12, 2006Date of Patent: July 6, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Patent number: 7707542Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.Type: GrantFiled: December 12, 2006Date of Patent: April 27, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Publication number: 20100033703Abstract: Mixed polarization state monitoring is presented. One method may include selecting a set of total dose values, and for each total dose value: exposing a location on a photoresist using illumination having an x-polarization value with an x-exposure dose ratio value of the total dose value, exposing the location on the photoresist using illumination having a y-polarization value with a y-exposure dose ratio value of the total dose value, and repeating the x-polarization value exposing and the y-polarization value exposing to achieve a range of mixed polarization states and a plurality of dose ratio values that range over extremes for the x-polarization exposure and the y-polarization exposure, each repeating occurring at a different location on the photoresist; and monitoring which mixed polarization states causes a change in an image printed at the different locations in the photoresist.Type: ApplicationFiled: August 11, 2008Publication date: February 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Gregory R. McIntyre
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Patent number: 7661087Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.Type: GrantFiled: December 12, 2006Date of Patent: February 9, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Patent number: 7653892Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.Type: GrantFiled: August 18, 2005Date of Patent: January 26, 2010Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Patent number: 7648802Abstract: The present invention presents three new classes of phase-shifting mask patterns. In optical image forming systems, a mask with phase shifted regions can act as a precision instrument for characterizing imaging. Three new classes of phase-shifting mask patterns have been invented to characterize projection printing tool illumination and phase-shifting mask (PSM) performance. The linear phase grating (LPG) and linear phase ring (LPR) both serve to characterize illumination angular distribution and uniformity. A third new class, the interferometric-probe monitor for phase-shifting masks (IPM-PSM), measures the effective phase, transmittance and edge effects of various phase-shifted mask features. All three patterns allow performance comparison across the field, tool-to-tool, over time, or to intended design.Type: GrantFiled: February 7, 2005Date of Patent: January 19, 2010Assignee: The Regents of the University of CaliforniaInventors: Andrew R. Neureuther, Gregory R. McIntyre
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Patent number: 7418693Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.Type: GrantFiled: August 18, 2005Date of Patent: August 26, 2008Assignee: Cadence Design Systems, Inc.Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
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Patent number: 7224458Abstract: A method to monitor the state of polarization incident on a photomask in projection printing is presented. The method includes a series of phase-shifting mask patterns that take advantage of high NA effects to create a signal dependent on only one incident polarization component. The patterns include in two embodiments a Radial Phase Grating (RPG) and Proximity Effect Polarization Analyzers (PEPA). A test reticle design includes multiple polarimeters with an array of pinholes on the backside of the photomask. This technique is able to monitor any arbitrary illumination scheme for a particular tool.Type: GrantFiled: February 16, 2006Date of Patent: May 29, 2007Assignee: The Regents of the University of CaliforniaInventors: Gregory R. McIntyre, Andrew R. Neureuther