Abstract: A master microprocessor downloads program codes to a slave microprocessor which does not require a read-only memory ROM containing any instruction codes. While downloading, the slave microprocessor reads the program instructions to execute from a register, which is written to by the master microprocessor. The execution of these instructions causes the slave microprocessor to write program instructions to its RAM which will be executed later, in normal operation. The slave microprocessor has a handshaked bus which causes it to terminate a read from the register only after the master microprocessor has written to it. Logic, preferably a programmable array logic (PAL) device, decodes addresses and generates the "READY" handshake bus signal for the slave microprocessor. The cost of the slave microprocessor is reduced since a bootloader ROM which may be embedded internal or external to the slave microprocessor integrated circuit chip is not required.