Abstract: A data transmission system includes a first data transmission device for receiving commands from a host; a second data transmission device for transmitting commands to a memory device; and a crossbar device for receiving commands from the first data transmission device over a first link and transmitting the commands to the second data transmission device over a second link. The crossbar device includes status logic to detect a command transmission error on the first link from the first data transmission device and transmits a retry command to prompt the first data transmission device to retry the transmission of the command over the first link. The second data transmission device reports a transmission error on the second link to the status logic of the crossbar device and the status logic of the crossbar device transmits the retry command to prompt the first data transmission device to retry the transmission of the command over the first link.

Abstract: In one embodiment of the present invention, a memory controller is provided that includes both a first processor and a second processor. If a memory device controlled by the controller indicates to the controller that an error condition exists in the device, either the first processor or the second processor is selected to handle the error condition. If the first processor is selected to handle the error condition, the first processor handles the error condition according to one or more statically preprogrammed error handling routines. Conversely, if the second processor is selected to handle the error condition, the second processor handles the error condition according to one or more dynamically programmable error handling routines.