Patents by Inventor Gregory S. Mathews
Gregory S. Mathews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200301615Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
-
Patent number: 10783104Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.Type: GrantFiled: October 7, 2019Date of Patent: September 22, 2020Assignee: Apple Inc.Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
-
Patent number: 10777252Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.Type: GrantFiled: August 22, 2018Date of Patent: September 15, 2020Assignee: Apple Inc.Inventors: Peter Fu, Gregory S. Mathews, Kai Lun Hsuing, Shane J. Keil
-
Patent number: 10678478Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: GrantFiled: August 24, 2018Date of Patent: June 9, 2020Assignee: Apple Inc.Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
-
Publication number: 20200159463Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
-
Publication number: 20200133905Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.Type: ApplicationFiled: October 7, 2019Publication date: April 30, 2020Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
-
Patent number: 10621115Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.Type: GrantFiled: June 29, 2018Date of Patent: April 14, 2020Assignee: Apple IncInventors: Gregory S. Mathews, Shane J. Keil, Lakshmi Narasimha Nukala
-
Publication number: 20200081652Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventors: Lakshmi Narasimha Murthy Nukala, Sukalpa Biswas, Thejasvi Magudilu Vijavaraj, Shane J. Keil, Gregory S. Mathews
-
Publication number: 20200081622Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.Type: ApplicationFiled: September 9, 2019Publication date: March 12, 2020Inventors: Gregory S. Mathews, Shane J. Keil, Sukalpa Biswas, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijavaraj
-
Publication number: 20200066328Abstract: A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Peter Fu, Gregory S. Mathews, Kai Lun Hsuing, Shane J. Keil
-
Publication number: 20200065028Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.Type: ApplicationFiled: August 24, 2018Publication date: February 27, 2020Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
-
Publication number: 20200057579Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
-
Patent number: 10545701Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.Type: GrantFiled: August 17, 2018Date of Patent: January 28, 2020Assignee: Apple Inc.Inventors: Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani, Sukalpa Biswas, Thejasvi Magudilu Vijayaraj, Yanzhe Liu, Shane J. Keil
-
Publication number: 20200004700Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Gregory S. Mathews, Shane J. Keil, Lakshmi Narasimha Nukala
-
Patent number: 10437758Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.Type: GrantFiled: June 29, 2018Date of Patent: October 8, 2019Assignee: Apple Inc.Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
-
Patent number: 10175905Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.Type: GrantFiled: September 13, 2016Date of Patent: January 8, 2019Assignee: Apple Inc.Inventors: Robert E. Jeter, Liang Deng, Kai Lun Hsiung, Manu Gulati, Rakesh L. Notani, Sukalpa Biswas, Venkata Ramana Malladi, Gregory S. Mathews, Enming Zheng, Fabien S. Faure
-
Publication number: 20180074743Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.Type: ApplicationFiled: September 13, 2016Publication date: March 15, 2018Inventors: Robert E. Jeter, Liang Deng, Kai Lun Hsiung, Manu Gulati, Rakesh L. Notani, Sukalpa Biswas, Venkata Ramana Malladi, Gregory S. Mathews, Enming Zheng, Fabien S. Faure
-
Patent number: 7876693Abstract: A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.Type: GrantFiled: June 4, 2003Date of Patent: January 25, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Gregory S. Mathews, Eric Anderson, Philip Ferolito, Mike Morrison
-
Patent number: 7801045Abstract: A network flow controller to manage network traffic bandwidth is described. Embodiments of the network flow controller include a hierarchical flow creditor, a proportional flow creditor, and a rate limiter. The hierarchical flow creditor is configured to manage a plurality of hierarchical credit accounts. The hierarchical credit accounts include a shared credit account associated with a plurality of distinct network traffic flows for a shared bandwidth resource. The proportional flow creditor is configured to track an oversubscription of the shared bandwidth resource by the plurality of distinct network traffic flows. The rate limiter is coupled to the hierarchical flow creditor and the proportional flow creditor. The rate limiter is configured to limit at least one of the distinct network traffic flows based on the oversubscription tracked by the proportional flow creditor.Type: GrantFiled: June 19, 2007Date of Patent: September 21, 2010Assignee: Alcatel LucentInventors: Gregory S. Mathews, Sanjay Jain
-
Patent number: 7733888Abstract: A prime number based pointer allocation technique. A packet-forwarding system incorporating the technique stores cells of a packet in packet memory, according to allocated pointers that have a fixed correspondence to locations in the packet memory. Each packet input interface of an ingress module has a memory parameter counter that is incremented by a different prime number each time a memory pointer is allocated to that input interface. The memory parameter counter includes a memory interface portion and a memory bank portion that correspond to the memory interfaces and memory banks of a packet memory with which the memory pointers are associated.Type: GrantFiled: May 22, 2003Date of Patent: June 8, 2010Assignee: Alcatel-Lucent USA Inc.Inventors: Gregory S. Mathews, Sanjay Jain, Jorge Alejandro Aguilar, Avinash Mani