Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Aspects of the invention include monitoring code coverage by executing a code sequence having a plurality of embedded markers. Aspects also include transmitting, upon encountering one of the plurality of embedded markers, a probing signal corresponding to the one of the plurality of embedded markers. Aspects further include obtaining, by a programmable data recorder, a debug level for the execution of the code sequence. Aspects also include storing the probing signal in a trace array based on a determination, by a programmable data recorder based on the debug level, that the probing signal should be recorded.

Abstract: Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency.

Abstract: Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: An apparatus includes a plurality of components and a plurality of component controllers. Each of the plurality of component controllers is associated with at least one component of the plurality of components. Each component controller is configured to compute a local power budget for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A service processor is configured to determine failure associated with at least one component controller of the plurality of component controllers or the at least one component associated with the at least one component controller. The service processor is configured to in response to a reset threshold not being exceeded, reset the at least one component controller without interrupting operations of any components of the at least one component that have not failed.

Abstract: Component power consumption is collected from each of a plurality of controllers of a node having a plurality of components. The component power consumption is provided to each of the plurality of controllers. A power differential is determined as a difference between a power cap for an apparatus and a total power consumption for the apparatus based, at least in part, on the component power consumption. A proportion of the total power consumption corresponding to the at least one component associated with the at least one component controller is determined. A local power budget is computed for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A failure associated with the at least one component controller or the at least one component is determined.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: Component power consumption is collected from each of a plurality of controllers of a node having a plurality of components. The component power consumption is provided to each of the plurality of controllers. A power differential is determined as a difference between a power cap for an apparatus and a total power consumption for the apparatus based, at least in part, on the component power consumption. A proportion of the total power consumption corresponding to the at least one component associated with the at least one component controller is determined. A local power budget is computed for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A failure associated with the at least one component controller or the at least one component is determined.

Abstract: An apparatus includes a plurality of components and a plurality of component controllers. Each of the plurality of component controllers is associated with at least one component of the plurality of components. Each component controller is configured to compute a local power budget for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A service processor is configured to determine failure associated with at least one component controller of the plurality of component controllers or the at least one component associated with the at least one component controller. The service processor is configured to in response to a reset threshold not being exceeded, reset the at least one component controller without interrupting operations of any components of the at least one component that have not failed.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A method for initializing processor cores in a multiprocessor system. The method includes a microcontroller initializing a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.

Abstract: A system and computer program product for initializing processor cores in a multiprocessor system. The system includes a microcontroller that initializes a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.

Abstract: A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.