Abstract: The present invention provides a method for driving a three-phase motor with a driver. The driver can provide a pulse-width modulated driving signal and a linear driving signal. The three-phase motor has a first leg, a second leg and a third leg. The method includes: connecting the second leg to the driver; floating the third leg; driving the second leg with the pulse-width-modulated driving signal from the driver; estimating a time when a voltage in the third leg will reach a predetermined threshold; and driving the second leg with the linear driving signal during that time.

Abstract: A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.

Abstract: The present invention provides a method for driving a three-phase motor with a driver. The driver can provide a pulse-width modulated driving signal and a linear driving signal. The three-phase motor has a first leg, a second leg and a third leg. The method includes: connecting the second leg to the driver; floating the third leg; driving the second leg with the pulse-width-modulated driving signal from the driver; estimating a time when a voltage in the third leg will reach a predetermined threshold; and driving the second leg with the linear driving signal during that time.

Abstract: One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

Abstract: One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

Abstract: A hard disk drive energy recovery circuit, a method of recovering energy from a motor of a hard disk drive and a hard disk drive. In one embodiment, the hard disk drive energy recovery circuit includes (1) a spindle resolver that generates transition signals as a spindle motor of the hard disk drive rotates among angular regions, (2) a spindle region state machine, coupled to the spindle resolver, that receives the transition signals and generates rectifier drive signals based thereon and (3) a synchronous rectifier, coupled to the spindle region state machine, that employs the rectifier drive signals to recover electrical energy from the motor.

Abstract: A method of detecting phase error between a phase current and a driving voltage includes generating a signal indicative of the phase current. The method includes identifying a time interval during which the signal indicative of the phase current is generally symmetric about a midpoint of the time interval when the phase error is approximately zero. The method further includes determining the extent to which the signal indicative of the phase current is symmetric about the midpoint of the time interval. Finally, in response to determining the extent to which the signal indicative of the phase current is symmetric, the method includes generating phase error information.