Abstract: Aspects of the disclosure can provide a bandpass transconductance amplifier that can include a minuend transconductance amplifier that converts a voltage signal to a first current and a subtrahend transconductance amplifier that converts the voltage signal to a second current having substantially the same amplitude as the first current but opposite polarity in both a first and a second stopband. The second current can have a substantially smaller amplitude than the first current in a passband. The disclosed bandpass transconductance amplifier can also include a controller that can tune the passband and the stopbands and a summing circuit that can add the first current and the second current.

Abstract: Aspects of the disclosure can provide a bandpass transconductance amplifier that can include a minuend transconductance amplifier that converts a voltage signal to a first current and a subtrahend transconductance amplifier that converts the voltage signal to a second current having substantially the same amplitude as the first current but opposite polarity in both a first and a second stopband. The second current can have a substantially smaller amplitude than the first current in a passband. The disclosed bandpass transconductance amplifier can also include a controller that can tune the passband and the stopbands and a summing circuit that can add the first current and the second current.

Abstract: A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node.

Abstract: The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.