Abstract: A data ordering system for use with personal computers having data pipelining capability is disclosed. The personal computer comprises a central processing unit (CPU) which issues data requests to one or more data exchange units, such as memory units or data Input/Output units. The data ordering system comprises a finite state machine (FSM) which receives inputs indicative of data requests transmitted by a central processing unit (CPU). The inputs cause the FSM to assume different output states which are indicative of the proper order of data requests. The state outputs of the FSM are used to enable or disable the transmission of data between the data exchange units and the CPU in order to insure the proper order of data responses to the issued data requests.

Abstract: A file server system provides increased bandwidth between a processor, a memory and a redundant array of inexpensive disks (RAID). The file server includes a processor connected to a processor bus. A first bridging circuit couples the processor bus to a peripheral bus. An array of disks is controlled by at least one disk controller. The disk controller is coupled to a local RAID bus. A second bridging circuit couples the local RAID bus to the processor bus independent of the first bridging circuit.

Abstract: An improved cooling system for a computer system includes a ventilated backplane for a disk drive cage. The backplane is rigidly secured to the rear of the disk drive cage and includes a plurality of apertures therein to permit convective heat transfer between the inner cavity of the drive cage and the main enclosure of the computer system. A fan assembly is attached to the backplane on the side opposite the drive cage to further enhance heat transfer through the ventilation apertures. In one embodiment, the fan assembly includes a plenum attached to the backplane and a fan attached to the plenum. In another embodiment, a fan housing is attached to the backplane and incorporates one or more fans therein.

Abstract: A method and apparatus provide a direct memory access (DMA) system that transfers data between a memory in a computer system and a plurality of I/O devices. The DMA system includes at least two channels which operate independently and in an interleaved manner so that multiple DMA transfers can occur concurrently. Each channel includes a pair of buffers so that data can be transferred between one buffer and memory at a rate determined by the memory and data can be transferred between the other buffer and the I/O device at a rate determined by the I/O device. Transfers between the two buffers occur at a data rate determined by the bus connecting the two buffers. Thus, the transfers between the two buffers occur in bursts to optimize the transfer and to reduce the amount of time that the bus is needed for the transfer. Therefore, the bus is available for transfers by the other DMA channel and by other devices on the bus.

Abstract: A data ordering system for use with personal computers having data pipelining capability is disclosed. The personal computer comprises a central processing unit (CPU) which issues data requests to one or more data exchange units, such as memory units or data Input/Output units. The data ordering system comprises a finite state machine (FSM) which receives inputs indicative of data requests transmitted by a central processing unit (CPU). The inputs cause the FSM to assume different output states which are indicative of the proper order of data requests. The state outputs of the FSM are used to enable or disable the transmission of data between the data exchange units and the CPU in order to insure the proper order of data responses to the issued data requests.