Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).

Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array.

Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.

Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Abstract: An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

Abstract: Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

Abstract: Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.

Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.

Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Abstract: A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.

Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.