Abstract: A memory device includes a memory; and at least one processor configured to: obtain a symbol stream including a plurality of symbols; determine a Huffman tree corresponding to the symbol stream, wherein each symbol of the plurality of symbols is assigned a corresponding prefix code from among a plurality of prefix codes based on the Huffman tree; generate a prefix length table based on the Huffman tree, wherein the prefix length table indicates a length of the corresponding prefix code for each symbol; generate a logarithm frequency table based on the prefix length table, wherein the logarithm frequency table indicates a logarithm of a frequency count for each symbol, generate a cumulative frequency table which indicates a cumulative frequency count corresponding to each symbol; generate a compressed bitstream by iteratively applying an encoding function to the plurality of symbols based on the logarithm frequency table and the cumulative frequency table; and store the compressed bitstream in the memory.

Abstract: A stormwater treatment device may include a crossflow settling device having a treatment channel defined by a front baffle, a rear baffle, and a pairs angled plates provided at supplementary angles therebetween and disposed between the front baffle and the rear baffle, the front baffle having a treatment channel opening and the rear baffle having a treatment channel outlet. Under normal flow, stormwater flows into the inlet and into the inlet chamber, into the treatment channel via the treatment channel opening, into the outlet chamber via the treatment channel outlet in a crossflow pattern causing the sediment to fall out of suspension, and out of the crossflow setting device through openings at the bottom of the pairs of angled plates.

Abstract: An identity authenticator receives a first authentication credential from a first application at a first computing device. The identity authenticator then determines that the first authentication credential is associated with a second authentication credential for the first application at a second computing device based on a stored authentication identity. The identity authenticator then provides a stored execution state for the first application to the first computing device, wherein the stored execution state is associated, based on the stored authentication identity, with at least one of the first authentication credential or the second authentication credential.

Abstract: A raised panel for the purpose of protecting stored items from moisture damage and promoting air circulation for use in storage units is disclosed.

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Abstract: In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.

Abstract: A series of substituted dicyclopropyl methyl derivatives as defined herein, being potent modulators of human IL-17 activity, are accordingly of benefit in the treatment and/or prevention of various human ailments, including inflammatory and autoimmune disorders.

Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Abstract: Embodiments include a microphone assembly comprising an array microphone and a housing configured to support the array microphone and sized and shaped to be mountable in a drop ceiling in place of at least one of a plurality of ceiling tiles included in the drop ceiling. A front face of the housing includes a sound-permeable screen having a size and shape that is substantially similar to the at least one of the plurality of ceiling tiles. Embodiments also include an array microphone system comprising a plurality of microphones arranged, on a substrate, in a number of concentric, nested rings of varying sizes around a central point of the substrate. Each ring comprises a subset of the plurality of microphones positioned at predetermined intervals along a circumference of the ring.

Abstract: A stormwater treatment device may include a chamber having a floor and a wall; an inlet formed in the wall that receives stormwater into an inlet side of the chamber; an outlet formed in the wall that discharges stormwater from an outlet side of the chamber; an enhanced settling device positioned in the outlet side of the chamber; a flow diverter plate in a lower portion of the chamber; and an outlet control diverter positioned proximate to the outlet. Stormwater is received by the inlet in a first flow direction, flows from the inlet side to the lower portion of the chamber in a second flow direction, flows through the enhanced settling device to an upper portion of the chamber in a third flow direction, flows through the outlet control diverter in fourth flow direction, and is discharged by the outlet in a fifth flow direction.

Abstract: A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Abstract: Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Abstract: Systems and methods for generating three-dimensional models with correlated three-dimensional and two dimensional imagery data are provided. In particular, imagery data can be captured in two dimensions and three dimensions. Imagery data can be transformed into models. Two-dimensional data and three-dimensional data can be correlated within models. Two-dimensional data can be selected for display within a three-dimensional model. Modifications can be made to the three-dimensional model and can be displayed within a three-dimensional model or within two-dimensional data. Models can transition between two dimensional imagery data and three dimensional imagery data.

Abstract: The present invention relates to dihydrocyclopenta-isoquinoline-sulfonamide derivatives of formula (I), processes for preparing them, pharmaceutical compositions containing them and their use in treating disorders caused by IgE (such as allergic responses, non-allergic mast cell responses or certain autoimmune responses), and in particular disorders caused by the interaction of IgE with the Fc?RI receptor.