Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.

Abstract: A semiconductor component includes a semiconductor chip, and a passive component, with the semiconductor component including a coil as the passive component. The semiconductor chip and the passive component are embedded in a plastic encapsulation compound with connection elements to external contacts.

Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.

Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.

Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.

Abstract: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.

Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.

Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.

Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

Abstract: Semiconductor element having a semiconductor chip and a passive component, as well as a method for its production The invention relates to a semiconductor component (1) having a semiconductor chip (2), and a passive component (3), with the semiconductor component (1) having a coil (6) as the passive component (3). The semiconductor chip (2) and the passive component (3) are embedded in a plastic encapsulation compound (4) with connection elements to external contacts (31).

Abstract: Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.