Patents by Inventor Grover C. Davidson, II
Grover C. Davidson, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10831539Abstract: Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.Type: GrantFiled: March 18, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Chad Collie, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20200301735Abstract: Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.Type: ApplicationFiled: March 18, 2019Publication date: September 24, 2020Inventors: Mathew Accapadi, Chad Collie, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 10572411Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: GrantFiled: June 25, 2018Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20180307637Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 10108453Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.Type: GrantFiled: June 30, 2016Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 10102037Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.Type: GrantFiled: June 30, 2016Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 10019392Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: GrantFiled: June 11, 2015Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 10019391Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: GrantFiled: March 20, 2015Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 9928157Abstract: A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.Type: GrantFiled: November 25, 2014Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20180004571Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Mathew ACCAPADI, Grover C. DAVIDSON, II, Dirk MICHEL, Bret R. OLSZEWSKI
-
Publication number: 20180004574Abstract: Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Mathew ACCAPADI, Grover C. DAVIDSON, II, Dirk MICHEL, Bret R. OLSZEWSKI
-
Patent number: 9465807Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: GrantFiled: October 18, 2013Date of Patent: October 11, 2016Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 9460101Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: GrantFiled: December 5, 2013Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20160275025Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: ApplicationFiled: June 11, 2015Publication date: September 22, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20160275024Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.Type: ApplicationFiled: March 20, 2015Publication date: September 22, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20160147653Abstract: A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Patent number: 9195601Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: GrantFiled: November 26, 2012Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
-
Patent number: 9038084Abstract: Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.Type: GrantFiled: February 23, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20150113226Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: ApplicationFiled: December 5, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
-
Publication number: 20150113225Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski