Patents by Inventor Grover G. Phillips

Grover G. Phillips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5822782
    Abstract: Methods and associated apparatus operable in a RAID subsystem to improve the speed and flexibility of initializing the subsystem by storing configuration and identification information in a reserved area on each disk drive in the subsystem. The reserved area on each disk drive of the disk array contains a unique identifier to identify the particular disk drive from all others and further contains group configuration information regarding all groups in which the particular disk drive is a member. The configuration and identification information is generated and written to each disk drive in the disk array when the particular disk drive is configured so as to be added or deleted from groups of the subsystem. Upon subsystem reset (e.g. power on reset or other reset operations), the RAID controller in the subsystem determines the proper configuration of the RAID groups despite temporary unavailability or physical relocation of one or more disk drives in the disk array.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: October 13, 1998
    Assignee: Symbios, Inc.
    Inventors: Donald R. Humlicek, John R. Kloeppner, Grover G. Phillips, Curtis W. Rink
  • Patent number: 5748871
    Abstract: An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: May 5, 1998
    Assignee: Symbios Logic Inc.
    Inventors: Keith B. DuLac, Grover G. Phillips
  • Patent number: 4181919
    Abstract: A decoding circuit including an adaptive synchronizing circuit for synchronizing to time-encoded data streams with an explicit output for eliminating non-data flux reversals in certain types of phase-encoded data such as Manchester-coded data. A preferred embodiment of the circuit includes a timer having first and second inputs and an output for producing a first state in response to a first signal at the first input, and also includes a means for producing a second state at the output of the timer in response to a predetermined condition at the second input. The circuit also includes additional circuit paths operatively coupling the output of the timer with the second input thereto whereby each of the first and second states are maintained at a relatively stable percentage of the time between successive first signals to the first input when the frequency of successive first signals varies. One of the first and second states of the timer provides a blanking pulse for eliminating the non-data flux reversals.
    Type: Grant
    Filed: March 28, 1978
    Date of Patent: January 1, 1980
    Assignee: NCR Corporation
    Inventor: Grover G. Phillips, Jr.