Abstract: A three-dimensional head portrait generating method executes on an electronic device. The three-dimensional head portrait generating method establishes a three-dimensional head portrait model with a plurality of feature points according to front face information, wherein feature points form a plurality of first grids on the three-dimensional head portrait model; maps a first part of the feature points of the three-dimensional head portrait model to a left face image to form a plurality of second grids on the left face image; maps a second part of the feature points of the three-dimensional head portrait model to a right face image to form a plurality of third grids on the right face image; and superimposes the left face image and the right face image onto the three-dimensional head portrait model according to a correspondence among the first grids, the second grids and the third grids, to generate a three-dimensional head portrait.

Abstract: A three-dimensional head portrait generating method executes on an electronic device. The three-dimensional head portrait generating method establishes a three-dimensional head portrait model with a plurality of feature points according to front face information, wherein feature points form a plurality of first grids on the three-dimensional head portrait model; maps a first part of the feature points of the three-dimensional head portrait model to a left face image to form a plurality of second grids on the left face image; maps a second part of the feature points of the three-dimensional head portrait model to a right face image to form a plurality of third grids on the right face image; and superimposes the left face image and the right face image onto the three-dimensional head portrait model according to a correspondence among the first grids, the second grids and the third grids, to generate a three-dimensional head portrait.

Abstract: An image processing method applied in an image processing device, which includes an image capturing unit, an image processing unit, an image recognition unit and an exposure adjusting unit, is provided. The image processing method includes the following steps: obtaining a first image by the image capturing unit, generating an average brightness of a dark part of the first image by the image processing unit; recognizing the first image by the image recognition unit; generating a first average brightness of a human face by the image processing unit and generating a first exposure value according to the average brightness of the dark part of the first image, the first average brightness of the human face and a weight array, when the human face is recognized from the first image; and adjusting an exposure of the first image according to the first exposure value by the exposure adjusting unit.

Abstract: An electronic device and a non-transitory computer readable storage medium are provided. After the real-time communication interface is enabled, the source filter obtains the image adjusting parameter when that the source filter is driven is detected. The source filter applies the image adjusting parameter to an image data captured by the image capturing unit, and then the adjusted image data is obtained. The real-time communication interface outputs the adjusted image data.

Abstract: A method to improve accuracy of a low voltage state in flash memory cells and the memory therewith is proposed. In the method, at least one memory cell is selected from among a plurality of memory cells in the non-volatile memory according to a first voltage and a second voltage. The first voltage is less than the second voltage and greater than or equal to an erase state voltage level of the flash memory, and the second voltage is less than or equal to a read voltage level of the flash memory. A recovery erase operation is applied to the at least one selected memory cell, thereby erasing electrical charges of the at least one selected memory cell to lower a threshold voltage of the at least one selected memory cell.

Abstract: An image processing method applied in an image processing device, which includes an image capturing unit, an image processing unit, an image recognition unit and an exposure adjusting unit, is provided. The image processing method includes the following steps: obtaining a first image by the image capturing unit, generating an average brightness of a dark part of the first image by the image processing unit; recognizing the first image by the image recognition unit; generating a first average brightness of a human face by the image processing unit and generating a first exposure value according to the average brightness of the dark part of the first image, the first average brightness of the human face and a weight array, when the human face is recognized from the first image; and adjusting an exposure of the first image according to the first exposure value by the exposure adjusting unit.

Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.

Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.