Patents by Inventor Guan-Wei Huang
Guan-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929273Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.Type: GrantFiled: July 27, 2020Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tsung-Sheng Kuo, Chih-Hung Huang, Guan-Wei Huang, Ping-Yung Yen, Hsuan Lee, Jiun-Rong Pai
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Publication number: 20230386939Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.Type: ApplicationFiled: August 14, 2023Publication date: November 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Publication number: 20230360939Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Inventors: Tsung-Sheng KUO, Guan-Wei HUANG, Chih-Hung HUANG, Yang-Ann CHU, Hsu-Shui LIU, Jiun-Rong PAI
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Patent number: 11791219Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: GrantFiled: November 7, 2022Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Patent number: 11721572Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.Type: GrantFiled: July 26, 2022Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Sheng Kuo, Guan-Wei Huang, Chih-Hung Huang, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
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Publication number: 20230095609Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.Type: ApplicationFiled: December 2, 2022Publication date: March 30, 2023Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
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Publication number: 20230058811Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Publication number: 20230054372Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Guan-Wei Huang, Yu-Shan Lu, Yu-Bey Wu, Jiun-Ming Kuo, Yuan-Ching Peng
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Patent number: 11527425Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.Type: GrantFiled: December 31, 2019Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
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Patent number: 11527448Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: GrantFiled: December 27, 2020Date of Patent: December 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Publication number: 20220359248Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Tsung-Sheng KUO, Guan-Wei HUANG, Chih-Hung HUANG, Yang-Ann CHU, Hsu-Shui LIU, Jiun-Rong PAI
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Patent number: 11488848Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.Type: GrantFiled: July 22, 2019Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Sheng Kuo, Guan-Wei Huang, Chih-Hung Huang, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
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Patent number: 11271090Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.Type: GrantFiled: May 6, 2020Date of Patent: March 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ming Kuo, Fu-Jung Chuang, Po-Jen Chuang, Chia-Wei Chang, Guan-Wei Huang, Chia-Yuan Chang
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Publication number: 20210320187Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.Type: ApplicationFiled: May 6, 2020Publication date: October 14, 2021Inventors: Chia-Ming Kuo, Fu-Jung Chuang, Po-Jen Chuang, Chia-Wei Chang, Guan-Wei Huang, Chia-Yuan Chang
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Publication number: 20210202277Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: Tsung-Sheng KUO, Yang-Ann CHU, Chih-Hung HUANG, Guan-Wei HUANG, Jiun-Rong PAI, Hsuan LEE
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Publication number: 20210118750Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: ApplicationFiled: December 27, 2020Publication date: April 22, 2021Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Publication number: 20210066104Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.Type: ApplicationFiled: July 27, 2020Publication date: March 4, 2021Inventors: Tsung-Sheng KUO, Chih-Hung HUANG, Guan-Wei HUANG, Ping-Yung YEN, Hsuan LEE, Jiun-Rong PAI
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Patent number: 10910277Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.Type: GrantFiled: February 26, 2020Date of Patent: February 2, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Patent number: 10892194Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.Type: GrantFiled: June 29, 2020Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
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Publication number: 20200328126Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng