Patents by Inventor Guang-Ren Shen
Guang-Ren Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11488946Abstract: A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error.Type: GrantFiled: January 15, 2021Date of Patent: November 1, 2022Assignee: Powertech Technology Inc.Inventors: Yi-hsin Chen, Guang-Ren Shen, Chia-Jen Chou
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Publication number: 20220130813Abstract: A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error.Type: ApplicationFiled: January 15, 2021Publication date: April 28, 2022Applicant: Powertech Technology Inc.Inventors: Yi-hsin Chen, Guang-Ren SHEN, Chia-Jen CHOU
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Patent number: 8604477Abstract: A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.Type: GrantFiled: April 18, 2011Date of Patent: December 10, 2013Assignee: Au Optronics CorporationInventors: Wu-Hsiung Lin, Po-Hsueh Chen, Shin-Shueh Chen, Guang-Ren Shen, Jia-Hong Ye
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Publication number: 20120241743Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Guang-Ren Shen, Pei-Ming Chen, Chun-Hsiun Chen, Wei-Ming Huang
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Patent number: 8232147Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.Type: GrantFiled: May 14, 2010Date of Patent: July 31, 2012Assignee: Au Optronics CorporationInventors: Guang-Ren Shen, Pei-Ming Chen, Chun-Hsiun Chen, Wei-Ming Huang
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Publication number: 20120138932Abstract: A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.Type: ApplicationFiled: April 18, 2011Publication date: June 7, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Wu-Hsiung Lin, Po-Hsueh Chen, Shin-Shueh Chen, Guang-Ren Shen, Jia-Hong Ye
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Patent number: 8154061Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.Type: GrantFiled: July 10, 2009Date of Patent: April 10, 2012Assignee: Au Optronics CorporationInventors: Chuan-Sheng Wei, Guang-Ren Shen, Chang-Yu Huang, Pei-Ming Chen, Sheng-Chao Liu, Chun-Hsiun Chen, Wei-Ming Huang
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Publication number: 20110215324Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.Type: ApplicationFiled: May 14, 2010Publication date: September 8, 2011Applicant: AU OPTRONICS CORPORATIONInventors: Guang-Ren Shen, Pei-Ming Chen, Chun-Hsiun Chen, Wei-Ming Huang
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Publication number: 20100270551Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.Type: ApplicationFiled: July 10, 2009Publication date: October 28, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Chuan-Sheng Wei, Guang-Ren Shen, Chang-Yu Huang, Pei-Ming Chen, Sheng-Chao Liu, Chun-Hsiun Chen, Wei-Ming Huang
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Publication number: 20070227892Abstract: A method for forming a fluid injection apparatus is disclosed. A patterned sacrificial layer is formed overlying a substrate. A electroplate seed layer is formed on the patterned sacrificial layer. A structural layer is formed overlying the electroplate seed layer and the substrate. The structural layer is patterned to form a nozzle. The electroplate seed layer in the nozzle is removed. The sacrificial layer is removed to form a fluid chamber. A protective layer is formed to selectively cover the structural layer and the electroplate seed layer.Type: ApplicationFiled: April 3, 2007Publication date: October 4, 2007Applicant: BENQ CORPORATIONInventors: Guang-Ren Shen, Wei-Lin Chen