Abstract: An image sensor includes at least a first row and a second row of photodiodes, each photodiode being coupled with an associated transistor, each associated transistor including a gate, the first and second row of photodiodes forming a series of 2×2 Bayer-pattern units. In each Bayer-pattern unit, a first photodiode and a second photodiode in the first row are designated respectively as a first green pixel and a blue pixel, and a third photodiode and a fourth photodiode in the second row are designated respectively as a red pixel and a second green pixel, wherein a position of the gate of the transistor associated with the first photodiode relative to the first photodiode and a position of the gate of the transistor associated with the fourth photodiode relative to the fourth photodiode are the same.

Abstract: The present invention provides a compact row decoder with multiple voltage support. The row decoder may include a global driver and a plurality of row-level drivers. The global driver may include one or more voltage level shifters that are operable to provide multiple voltages required to drive each of the plurality of row-level drivers. The plurality of row-level drivers each may include only one voltage level shifter. In an example, the row-level driver includes an address decoder implemented in a digital domain providing an address selection signal, a voltage level shifter to convert the address selection signal to an analog domain, and a tow driver receiving driving signals from the global driver. The row driver has no voltage level shifter contained therein. Thus, the row-level drivers and the row decoder may be very compact. The present invention further provides a CMOS image sensor including the row decoder and a method of operating the CMOS image sensor.

Abstract: A system and method is provided for image sensing. The image sensing system includes a comparator for comparing an input signal representing a sensed light signal from at least one pixel of the image sensing system and a reference signal. The comparator includes at least one digital transistor.

Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

Abstract: The present invention relates to an integrated circuit having a flexible reference. In an example, the integrated circuit includes a reference generator, and the reference generator can generate a flexible reference signal in response to a control signal. The flexible reference signal can be changed freely by adjusting the control signal. By providing the flexible reference, the present invention can enhance the capability of verification and characterization for an integrated circuit design and reduce the physical layout area of the integrated circuit design.

Abstract: The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X?1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin?X(Vin?Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.

Abstract: Capturing a target image includes activating a first image sensor for capturing the target image. A sequence of images is captured with a second image sensor while the first image sensor remains activated. A determination is made as to whether the sequence of images captured by the second image sensor includes a shutter gesture while the first image sensor remains activated. If a shutter gesture is included in the sequence of images captured by the second image sensor, the first image sensor captures the target image in response.

Abstract: An apparatus includes analog-to-digital (A/D) conversion circuitry coupled to a pixel array. The A/D conversion circuitry includes a voltage ramp generator and a set of column A/D conversion circuits. The voltage ramp generator generates a single slope voltage ramp in a first state and a multiple slope voltage ramp in a second state. The set of column A/D conversion circuits is coupled with the voltage ramp generator. The apparatus further includes calibration circuitry coupled with the set of column A/D conversion circuits and operable to determine digital calibration data to adjust digital image data. The calibration circuitry provides analog calibration data that spans a calibration range to the set of column A/D conversion circuits instead of the analog image data from the pixel array being provided to the set of column A/D conversion circuits.

Abstract: An apparatus includes analog-to-digital (A/D) conversion circuitry coupled to a pixel array. The A/D conversion circuitry includes a voltage ramp generator and a set of column A/D conversion circuits. The voltage ramp generator generates a single slope voltage ramp in a first state and a multiple slope voltage ramp in a second state. The set of column A/D conversion circuits is coupled with the voltage ramp generator. The apparatus further includes calibration circuitry coupled with the set of column A/D conversion circuits and operable to determine digital calibration data to adjust digital image data. The calibration circuitry provides analog calibration data that spans a calibration range to the set of column A/D conversion circuits instead of the analog image data from the pixel array being provided to the set of column A/D conversion circuits.

Abstract: A method of capturing an image includes activating a first image sensor and capturing a sequence of images with a second image sensor. A determination is made as to whether the sequence of images captured by the second image sensor includes a shutter gesture. If a shutter gesture is included in the sequence of images captured by the second image sensor, the first image sensor captures a target image in response.

Abstract: A circuit for providing signal amplification with reduced fixed pattern noise. In an embodiment, the circuit includes an amplifier and a plurality of legs coupled in parallel with one another between a first node for an input of the amplifier and a second node for an output of the amplifier. Control logic selects a first combination of the plurality of legs for a first configuration of the circuit to provide a first loop gain with the amplifier. In another embodiment, the control logic further selects a second combination of the plurality of legs for a second configuration of the circuit to provide a second loop gain with the amplifier, wherein the first loop gain is substantially equal to the second loop gain.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: An example image sensor includes a plurality of pixels arranged in an array of columns and rows, a row driver, and a control logic circuit. The row driver is coupled to pixels in a row of the array to provide a variable driving voltage to drive transistors included in the pixels of the row. The control logic circuit is coupled to provide one or more control logic signals to the row driver. The row driver adjusts a magnitude of the driving voltage in response to the one or more control logic signals.

Abstract: Embodiments of an image sensor including a pixel array with a plurality of pixels arranged into rows and columns. Control circuitry coupled to the pixels in each row, and an analog-to-digital converter is coupled to the pixels in each column of the pixel array. Each analog-to-digital converter includes a ramp comparator, and a variable current source coupled to the ramp comparator to provide a variable bias current to the ramp comparator. The bias current can adjusted during reading of a row of pixels according to a dynamic bias current profile that maintains at least a specified margin between the random noise of the pixels and an acceptable noise level. Other embodiments are disclosed and claimed.

Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: A comparator circuit for generating a signal representing a comparison of an input signal and a reference signal. In an embodiment, the comparator circuit includes a first stage and a second stage to provide respective signal amplification, where switch circuitry of the second stage switchedly couples respective elements of the first and second stages. The comparator circuit further includes a third stage to generate an output signal based on an intermediate signal of the second stage. In another embodiment, feedback circuitry of the comparator circuit is to selectively control a voltage of the output stage based on the output signal.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values.

Abstract: A technique for obtaining a corrected pixel value is disclosed. The technique includes measuring a first dark current of a dark calibration pixel of a pixel array and measuring a second dark current of an imaging pixel of the pixel array. A dark current ratio is calculated based on the first dark current and the second dark current. An image charge is acquired with the imaging pixel where the image charge is accumulated over a first time period. A charge is acquired with the dark calibration pixel where the charge is accumulated over a second time period. The second time period is approximately equal to the first time period divided by the dark current ratio. A corrected imaging pixel value is calculated using a first readout from the imaging pixel and a second readout from the dark calibration pixel.