Abstract: An online system maintains item embeddings for items. As a number of items maintained by the online system increases, maintaining a single index of the item embeddings is increasingly difficult. To increase scalability, the online system partitions item embeddings into multiple indices, with each index corresponding to a value of a specific attribute maintained by the online system for items. For example, an online system generates indices that each correspond to a different warehouse offering items. To expedite retrieval of item embeddings, the online system allocates each index to one of a number of shards. When the online system receives a query, the online system determines an embedding for the query and retrieves an index from a shard based on metadata received with the query. Based on distances between the query for the embedding and the item embeddings in the retrieved index, the online system selects one or more items.

Abstract: An online system maintains various items and maintains values for different attributes of the items, as well as an item embedding for each item. When the online system receives a query for retrieving one or more items, the online system generates an embedding for the query. Based on measures of similarity between the embedding for the query and item embeddings, the online system selects a set of items. The online system identifies a specific attribute of items and generates a whitelist of values for the specific attribute based on measures of similarity between item embeddings for items in the selected set and the embedding for the query. The online system removes items having values for the selected attribute outside of the whitelist of values from the selected set of items to identify items more likely to be relevant to the query.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Abstract: The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles.

Abstract: We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Abstract: The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles.

Abstract: During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator.

Abstract: A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

Abstract: An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.