Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Abstract: This present disclosure provides a core-shell quantum dot, a preparation method thereof, and a light-emitting device containing the same. The core of the core-shell quantum dot is CdSeXS(1-X), and the quantum dot shells include a first shell and a second shell, the first shell being selected from one or more of ZnSe, ZnSeYS(1-Y) and Cd(Z)Zn(1-Z)S, the second shell covering the first shell being one of Cd(Z)Zn(1-Z)S and ZnS, the maximum emission peak of the core-shell quantum dot is less than or equal to 480 nm, 0<X<1, 0<Y<1, 0<Z<1. The CdSeXS(1-X) core has a smaller bandgap and a shallower HOMO energy level, making hole injection easier.

Abstract: An example microelectronics device package includes: a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, the uppermost trace conductor layer having a first pattern density. The device mounting layer includes a device connection conductor layer; a device mounting land conductor layer on the device connection conductor layer, the device mounting land conductor layer having device mounting land conductors directly contacting the conductors of the device connection conductor layer and having a second pattern density that is less than the first pattern density. A semiconductor die is flip chip mounted to the device mounting layer by solder joints between post connects extending from the semiconductor die and the device mounting land conductors. Mold compound covers the semiconductor die, and the device mounting layer, the mold compound is spaced from the uppermost trace conductor layer by the device mounting layer.

Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Abstract: Provided are a nanocrystalline, a preparation method and a composition, an optical film, and a light emitting device. The nanocrystalline comprises an initial nanocrystalline and a sacrificial shell layer coated outside of the initial nanocrystalline. The sacrificial shell layer comprises n sacrificial sub-layers sequentially coated outward from the initial nanocrystalline at the center. The n sacrificial sub-layers may be of the same material or different materials. If the nanocrystalline is etched, at least a portion of the sacrificial shell layer is gradually consumed during the etching process. The following are measured m times during the etching process: the fluorescence emission wavelength, the full width at half maximum, the quantum yield, and the absorbance under excitation of an excitation light of a certain wavelength are measured, wherein 0?MAXPL?MINPL?10 nm, 0?MAXFWHM?MINFWHM?10 nm, 80%?MINQY/MAXQY?100%, and 80%?MINAB/MAXAB?100%, and n and m are integers greater than or equal to 1.

Abstract: An electronic device with a multilevel package substrate having multiple levels including a first level having conductive leads and a final level having conductive landing areas along a side, as well as a die mounted to the multilevel package substrate and having conductive terminals electrically coupled to respective ones of the conductive leads, and a package structure that encloses the die and a portion of the multilevel package substrate, where the multilevel package substrate has a conductive elevated trace layer with a confinement feature that extends outward from the side of the final level along a third direction that is orthogonal to the first and second directions, the confinement feature having a sidewall configured to laterally confine one of a solder, an adhesive, a side of a passive component, and a side of the die.

Abstract: Provided is an application deployment method, including: receiving an application blueprint (S1) including at least two different sub-blueprints; and deploying an application instance on a hardware device in a cluster according to the application blueprint and external capabilities provided by all deployed application instances (S2), with a sum of the external capabilities provided by all the deployed application instances being greater than or equal to the total external capability of the application. The present disclosure further provides an application blueprint generation method, a microservice platform, a communication terminal and a computer-readable medium.

Abstract: The present disclosure relates to a quantum dot and a preparation method for the same, and a photoelectric device. The quantum dot includes a core and a shell layer coating the core, a material of the core is CdZnSe, and a material of the shell layer is CdZnS, wherein, a molar ratio of Cd element with respect to S element in the shell layer is from 0.15:1 to 0.4:1.

Abstract: A memory motor winding multiplexing control method and system for flux linkage observation. The method comprises the following steps: I: when the magnetization state of a memory motor needs to be adjusted, selecting a flux regulation current reference value according to a rotation speed of the motor; II: by means of current feedback control, driving a direct-current flux regulation winding to generate a flux regulation current so as to adjust the magnetization state of a permanent magnet; III: when the memory motor is operating normally, collecting an induction voltage of the flux regulation winding and extracting an induced electromotive force of the flux regulation winding; and IV: using the induced electromotive force of the flux regulation winding to calculate the flux linkage of the permanent magnet for vector control of the motor.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: A memory motor winding multiplexing control method and system for flux linkage observation. The method comprises the following steps: I: when the magnetization state of a memory motor needs to be adjusted, selecting a flux regulation current reference value according to a rotation speed of the motor; II: by means of current feedback control, driving a direct-current flux regulation winding to generate a flux regulation current so as to adjust the magnetization state of a permanent magnet; III: when the memory motor is operating normally, collecting an induction voltage of the flux regulation winding and extracting an induced electromotive force of the flux regulation winding; and IV: using the induced electromotive force of the flux regulation winding to calculate the flux linkage of the permanent magnet for vector control of the motor.

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Abstract: This present disclosure provides a core-shell quantum dot, a preparation method thereof, and a light-emitting device containing the same. The core of the core-shell quantum dot is CdSeXS(1-X), and the quantum dot shells include a first shell and a second shell, the first shell being selected from one or more of ZnSe, ZnSeYS(1-Y) and Cd(Z)Zn(1-Z)S, the second shell covering the first shell being one of Cd(Z)Zn(1-Z)S and ZnS, the maximum emission peak of the core-shell quantum dot is less than or equal to 480 nm, 0<X<1, 0<Y<1, 0<Z<1. The CdSeXS(1-X) core has a smaller bandgap and a shallower HOMO energy level, making hole injection easier.

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

Abstract: A described example includes a package substrate having an array of die pads arranged in rows and columns on a die mount surface, and having an opposing board side surface; a solder mask layer overlying the die mount surface; a first plurality of solder mask defined openings in the solder mask layer at die pad locations, the solder mask defined openings exposing portions of a surface of corresponding die pads, the surface facing away from the package substrate; and at least one non-solder mask defined opening in the solder mask layer at a die pad location, exposing the entire surface of the die pad and sidewalls of the die pad at the non-solder mask defined opening.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.