Patents by Inventor Gudoor Reddy

Gudoor Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MIMCAP architecture
    Patent number: 11476186
    Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: October 18, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ramaprasath Vilangudipitchai, Gudoor Reddy, Samrat Sinharoy, Smeeta Heggond, Anil Kumar Koduru, Kamesh Medisetti, Seung Hyuk Kang
  • MIMCAP ARCHITECTURE
    Publication number: 20210391249
    Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 16, 2021
    Inventors: Ramaprasath VILANGUDIPITCHAI, Gudoor REDDY, Samrat SINHAROY, Smeeta HEGGOND, Anil Kumar KODURU, Kamesh MEDISETTI, Seung Hyuk KANG
  • Adaptive multi-tier power distribution grids for integrated circuits
    Patent number: 10956645
    Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy
  • ADAPTIVE MULTI-TIER POWER DISTRIBUTION GRIDS FOR INTEGRATED CIRCUITS
    Publication number: 20190220571
    Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy
  • Adaptive multi-tier power distribution grids for integrated circuits
    Patent number: 10318694
    Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy
  • ADAPTIVE MULTI-TIER POWER DISTRIBUTION GRIDS FOR INTEGRATED CIRCUITS
    Publication number: 20180144086
    Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.
    Type: Application
    Filed: February 14, 2017
    Publication date: May 24, 2018
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy