Abstract: A service processor is provided that includes a processor, a memory coupled to the processor and having instructions for executing an operating system kernel having an integrity management subsystem, secure boot firmware, and a tamper-resistant secure trusted dedicated microprocessor. The secure boot firmware performs a secure boot operation to boot the operating system kernel of the service processor. The secure boot firmware records first measurements of code executed by the secure boot firmware when performing the boot operation, in one or more registers of the tamper-resistant secure trusted dedicated microprocessor. The operating system kernel enables the integrity management subsystem. The integrity management subsystem records second measurements of software executed by the operating system kernel, in the one or more registers of the tamper-resistant secure trusted dedicated microprocessor.

Abstract: A secure computer architecture is provided. With this architecture, data is received, in a component of an integrated circuit chip implementing the secure computer architecture, for transmission across a data communication link. The data is converted, by the component, to one or more first fixed length frames. The one or more first fixed length frames are then transmitted, by the component, on the data communication link in a continuous stream of frames. The continuous stream of frames includes one or more second fixed length frames generated when no data is available for inclusion in the frames of the continuous stream.

Abstract: A blockchain may include various transactions which are identified and which require processing. The order of processing such transactions may be optimized by examining content of the transactions. One example method of operation may comprise one or more of receiving an ordered set of proposed transactions intended for inclusion in a blockchain block, creating a lattice structure containing the proposed transactions for the blockchain block, the lattice structure comprising a top and a bottom and a plurality of nodes representing the proposed transactions, determining an order of execution of the proposed transactions for the blockchain block via the lattice structure, and processing the proposed transactions in the lattice structure in parallel based on a configuration of the lattice structure.

Abstract: A certified checkpoint is provided for a ledger comprising a blockchain and a world state. The certified checkpoint enables a third party to recognize and verify that the ledger has integrity, a known starting state, and immutability properties starting at a specific point in time. Certification means that all of the validating peers reached consensus on the state of the ledger at that point in time. Thus, the certified checkpoint state represents an agreed-upon state, and that one or more subsequent operations on the ledger are relative to that agreed-upon state. Preferably, before a checkpoint is certified, it must be consistent, meaning that all validating peers have reached the same value for the checkpoint. Preferably, the checkpoint is a compression of the current blockchain world state into a compact representation (e.g., a hash) of the ledger that based on an agreed-upon consensus protocol is consistent across the (validating) peers. A technique to certify a blockchain checkpoint also is described.

Abstract: A certified checkpoint is provided for a ledger comprising a blockchain and a world state. The certified checkpoint enables a third party to recognize and verify that the ledger has integrity, a known starting state, and immutability properties starting at a specific point in time. Certification means that all of the validating peers reached consensus on the state of the ledger at that point in time. Thus, the certified checkpoint state represents an agreed-upon state, and that one or more subsequent operations on the ledger are relative to that agreed-upon state. Preferably, before a checkpoint is certified, it must be consistent, meaning that all validating peers have reached the same value for the checkpoint. Preferably, the checkpoint is a compression of the current blockchain world state into a compact representation (e.g., a hash) of the ledger that based on an agreed-upon consensus protocol is consistent across the (validating) peers.

Abstract: A certified checkpoint is provided for a ledger comprising a blockchain and a world state. The certified checkpoint enables a third party to recognize and verify that the ledger has integrity, a known starting state, and immutability properties starting at a specific point in time. Certification means that all of the validating peers reached consensus on the state of the ledger at that point in time. Thus, the certified checkpoint state represents an agreed-upon state, and that one or more subsequent operations on the ledger are relative to that agreed-upon state. Preferably, before a checkpoint is certified, it must be consistent, meaning that all validating peers have reached the same value for the checkpoint. Preferably, the checkpoint is a compression of the current blockchain world state into a compact representation (e.g., a hash) of the ledger that based on an agreed-upon consensus protocol is consistent across the (validating) peers. The approach also is extended to a permissionless blockchain.

Abstract: Included within a shared housing are at least one user interface element; a first isolated computational entity; a second isolated computational entity; and a switching arrangement. The switching arrangement is configured to, in a first mode, connect the first isolated computational entity to the at least one user interface element; and, in a second mode, connect the second isolated computational entity to the at least one user interface element.

Abstract: Included within a shared housing are at least one user interface element; a first isolated computational entity; a second isolated computational entity; and a switching arrangement. The switching arrangement is configured to, in a first mode, connect the first isolated computational entity to the at least one user interface element; and, in a second mode, connect the second isolated computational entity to the at least one user interface element.

Abstract: Included within a shared housing are at least one user interface element; a first isolated computational entity; a second isolated computational entity; and a switching arrangement. The switching arrangement is configured to, in a first mode, connect the first isolated computational entity to the at least one user interface element; and, in a second mode, connect the second isolated computational entity to the at least one user interface element.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: Disclosed are a processor and processing method that provide non-hierarchical computer security enhancements for context states. The processor can comprise a context control unit that uses context identifier tags associated with corresponding contexts to control access by the contexts to context information (i.e., context states) contained in the processor's non-stackable and/or stackable registers. For example, in response to an access request, the context control unit can grant a specific context access to a register only when that register is tagged with a specific context identifier tag. If the register is tagged with another context identifier tag, the contents of the specific register are saved in a context save area of memory and the previous context states of the specific context are restored to the specific register before access can be granted.

Abstract: This invention provides for the hierarchical provisioning and management of a computing infrastructure which is used to provide computing services to the customers of the service provider that operates the infrastructure. Infrastructure resources can include those acquired from other service providers. The invention provides architecture for hierarchical management of computing infrastructures. It allows the dynamic provisioning and assignment of resources to computing environments. Customers can have multiple computing environments within their domain. The service provider shares its resources across multiple customer domains and arbitrates on the use of resources between and within domains. The invention enables resources to be dedicated to a specific customer domain or to a specific computing environment. Customers can specify acquisition and distribution policy which controls their use of resources within their domains.

Abstract: Included within a shared housing are at least one user interface element; a first isolated computational entity; a second isolated computational entity; and a switching arrangement. The switching arrangement is configured to, in a first mode, connect the first isolated computational entity to the at least one user interface element; and, in a second mode, connect the second isolated computational entity to the at least one user interface element.

Abstract: A secure computer architecture is provided. With this architecture, data is received, in a component of an integrated circuit chip implementing the secure computer architecture, for transmission across a data communication link. The data is converted, by the component, to one or more first fixed length frames. The one or more first fixed length frames are then transmitted, by the component, on the data communication link in a continuous stream of frames. The continuous stream of frames includes one or more second fixed length frames generated when no data is available for inclusion in the frames of the continuous stream.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: A recursive logical partition real memory map mechanism is provided for use in address translation. The mechanism, which is provided in a data processing system, receives a first address based on an address submitted from a process of a currently active logical partition. The first address is translated into a second address using a recursive logical partition real memory (RLPRM) map data structure for the currently active logical partition. The memory is accessed using the second address. The RLPRM map data structure provides a plurality of translation table pointers, each translation table pointer pointing to a separate page table for a separate level of virtualization in the data processing system with the data processing system supporting multiple levels of virtualization.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.