Abstract: The invention relates to an arrangement for coating or etching substrates. In this arrangement an HF substrate bias voltage is generated without contact. For this purpose plasma sources are equipped with a bias pot which is disposed at the dark space distance from a substrate carrier and acted upon by HF. Depending on the source used, the bias pot can be constructed as an independent unit or as a component part of the source connected so as to be conducting-for example as an HF magnetron. Via this coupled-in HF power the dc potential on the carrier, and consequently the ion bombardment on the substrate, can be set specifically.

Abstract: The invention relates to an electrode configuration for a device for generating a plasma. RF is coupled contactlessly via a capacitive coupling electrode disposed at the dark space distance into a carrier backside of a coating installation. Dark space shields on the coating side define the plasma zone and prevent the formation of parasitic plasmas. HF substrate bias voltage on the moving substrate carrier is achieved with a defined plasma zone and the development of parasitic plasmas is avoided.

Abstract: A method of producing an electrophotographic recording material, in which an aluminum substrate is coated with a blocking layer. The blocking layer is coated with a layer of amorphous silicon by direct current magnetron cathode sputtering. At least one sputter target containing silicon is used, and a power density of from about 2.0 W/cm.sup.2 to about 30 W/cm.sup.2 is used for the sputtering. The sputtering is performed in an atmosphere containing hydrogen and an inert gas, with a total pressure of inert gas and hydrogen being in a range from about 1.times.10.sup.-3 to about 10.times.10.sup.-3 mbar. This produces a layer of amorphous silicon having a hydrogen content of more than 40 atom %, an inert gas content in a range of 0.01 to 10 atom %, and in which the relative peak heights of the low and high temperature peaks during hydrogen effusion are approximately equal. The amorphous silicon layer is then coated with a cover layer.