Patents by Inventor Guillermo Rozas

Guillermo Rozas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060220678
    Abstract: A method for configuring a signal path within a digital integrated circuit. The method includes transmitting an output from a first logic module, receiving the output at a second logic module, and conveying the output from the first logic module to the second logic module by using a configurable signal path. The configurable signal path is variable by selectively including at least one latch.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Applicant: TRANSMETA CORPORATION
    Inventors: Guillermo Rozas, Robert Masleid
  • Publication number: 20060179483
    Abstract: Validating a computer system. An integrity check program is declared during booting of the computer system. It is determined whether the integrity check program quasi-periodically validates dynamic data structures of an operating system within a time interval.
    Type: Application
    Filed: February 7, 2005
    Publication date: August 10, 2006
    Inventor: Guillermo Rozas
  • Publication number: 20060179308
    Abstract: A system and method for providing a secure boot architecture, in accordance with one embodiment of the present invention, includes a processor having an atomic state machine and a physically protected storage area. The atomic state machine stores a state of the processor in a state save map upon a boot-mode event. The atomic state machine also authenticates an object of a Pre-BIOS Boot Vector Region (PBBVR) in response to the boot-mode event. The PBBVR may be stored in the physically protected storage area. The atomic state machine loads the PBBVR from the physically protected storage area into an overlay memory if the PBBVR is successfully authenticated. The processor executes the PBBVR from the overlay memory if the PBBVR is successfully authenticated.
    Type: Application
    Filed: February 7, 2005
    Publication date: August 10, 2006
    Inventors: Andrew Morgan, Christian Ludloff, Guillermo Rozas
  • Publication number: 20050010739
    Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
    Type: Application
    Filed: July 28, 2003
    Publication date: January 13, 2005
    Inventors: Guillermo Rozas, Alexander Klaiber, H. Anvin, David Dunn
  • Patent number: 6748589
    Abstract: A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: June 8, 2004
    Assignee: Transmeta Corporation
    Inventors: Richard Johnson, Guillermo Rozas
  • Patent number: 6725361
    Abstract: A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: April 20, 2004
    Assignee: Transmeta Corporation
    Inventors: Guillermo Rozas, David Dunn, David Dobrikin, Alex Klaiber, Daniel H. Nelsen
  • Patent number: 6470339
    Abstract: A software system that provides access control to resources and that disassociates access rights to resources from references to resources to prevent the formation of large and unwieldy access control lists and to enable advanced decentralized security controls. The software system includes a repository that holds a resource descriptor for each resource including lock/permission pairs. Access to particular resources or groups of resources is provided by providing users with the appropriate keys. The keys are themselves are resources with resource descriptors in the repository. Access rights for users may be revoked by deleting keys from the repository. The software system also provides visibility fields for compartmentalizing access to resources. In addition, the software system provides authorizers that maintain audit trails when critical resource such as keys are passed among users and that enable advanced security control when passing resources among users.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: October 22, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Alan H. Karp, Rajiv Gupta, Arindam Banerji, Chia-Chiang Chao, Ernest Mak, Sandeep Kumar, Venkatesh Krishnan, Guillermo Rozas
  • Patent number: 6205466
    Abstract: A software infrastructure for providing an open digital services marketplace including a naming manager that enables a requesting task to refer to a desired resource using a name which is local to the requesting task and a router that forwards the request to an appropriate handler for the desired resource and that enables at least one additional task to be invoked in response to the request. The infrastructure includes a permission manager that compares a set of access rights of the requesting task to the desired resource to a set of permissions associated with the desired resource such that the access rights are kept separately from the reference to the desired resource. The desired resource, the requesting task, the additional task, and a set of additional components used to handle the request are each modeled as a resource defined by a corresponding set of meta-data which includes a set of attributes and a reference to a grammar for interpreting the attributes.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: March 20, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Alan H. Karp, Rajiv Gupta, Arindam Banerji, Ernest Mak, Sandeep Kumar, Guillermo Rozas, Chia-Chiang Chao, Venkatesh Krishnan, Alexandre Bronstein