Patents by Inventor Guk-Hwan AN

Guk-Hwan AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240173543
    Abstract: Proposed is a vagus nerve stimulator having at least two electrodes that are configured to be worn on at least one of the left and right ears and are configured to generate electrical stimulation on the vagus nerve in the auricle. The vagus nerve stimulator may include: a body part configured to be located on a side of a wearer's ear; a first electrode configured to be inserted into and make contact with the external acoustic meatus of the wearer's ear; a second electrode configured to make contact with the cymba concha of the wearer's ear; a first electrode fixing part protruding from the body part and having a first electrode at an end thereof; and a second electrode fixing part protruding from the body part and having a second electrode at an end thereof.
    Type: Application
    Filed: December 1, 2021
    Publication date: May 30, 2024
    Applicant: NEURIVE Co., Ltd.
    Inventors: Jae Jun SONG, Hyuk CHOI, Guk Han KIM, Yong Ho JUNG, Ki Hwan HONG
  • Patent number: 11996444
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: May 28, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan Kim
  • Publication number: 20240047214
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Patent number: 11830740
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 28, 2023
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan Kim
  • Publication number: 20230006039
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Publication number: 20230005748
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Application
    Filed: September 9, 2022
    Publication date: January 5, 2023
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Publication number: 20220328619
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 13, 2022
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Patent number: 11430863
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 30, 2022
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan Kim
  • Publication number: 20220052156
    Abstract: A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer.
    Type: Application
    Filed: July 15, 2021
    Publication date: February 17, 2022
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Patent number: 11171222
    Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 9, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Guk Hwan Kim, Jin Yeong Son
  • Publication number: 20210313420
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 7, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Publication number: 20210242024
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Patent number: 11018010
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 25, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan Kim
  • Publication number: 20200312666
    Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.
    Type: Application
    Filed: August 1, 2019
    Publication date: October 1, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan KIM
  • Publication number: 20200251575
    Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.
    Type: Application
    Filed: May 31, 2019
    Publication date: August 6, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Guk Hwan KIM, Jin Yeong SON
  • Patent number: 10727300
    Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Guk Hwan Kim, Jin Yeong Son
  • Patent number: 10428458
    Abstract: The present invention relates to a medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers as prepared by the paper making process, a preparation method thereof, and an adhesion prevention barrier using the same. The present invention provides a single phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, to induce capillary action of micropores formed between the fibers and thereby control the gelation time, and provides a composite nonwoven fabric formed by laminating a nonwoven fabric layer comprising a different kind of biodegradable polymer material not susceptible to gelation on the single-phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, thereby improving dimensional stability and convenience of surgical procedure. The present invention further provides a dyed medical nonwoven fabric to improve visibility, allowing easiness of recognizing the placement or location of the medical nonwoven fabric.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: October 1, 2019
    Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Jung Nam Im, Dae Young Lim, Guk-Hwan An, Yoon Jin Kim
  • Publication number: 20190019866
    Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.
    Type: Application
    Filed: January 12, 2018
    Publication date: January 17, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Guk Hwan KIM, Jin Yeong SON
  • Publication number: 20160153143
    Abstract: The present invention relates to a medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers as prepared by the paper making process, a preparation method thereof, and an adhesion prevention barrier using the same. The present invention provides a single phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, to induce capillary action of micropores formed between the fibers and thereby control the gelation time, and provides a composite nonwoven fabric formed by laminating a nonwoven fabric layer comprising a different kind of biodegradable polymer material not susceptible to gelation on the single-phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, thereby improving dimensional stability and convenience of surgical procedure. The present invention further provides a dyed medical nonwoven fabric to improve visibility, allowing easiness of recognizing the placement or location of the medical nonwoven fabric.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: Jung Nam Im, Dae Young Lim, Guk-Hwan An, Yoon Jin Kim
  • Publication number: 20150234799
    Abstract: An apparatus and method of operating a text related function are provided. The apparatus includes receiving a selection of at least one text region from displayed text, determining at least one classification for one of the at least one text region and the character information based on a connection relationship between at least one piece of character information included in the at least one text region selected, and processing a text related function associated with the at least one piece of character information according to the determined at least one classification.
    Type: Application
    Filed: January 28, 2015
    Publication date: August 20, 2015
    Inventors: Guk Hwan CHO, Ki Chul SONG, Ji Woo LEE, In Soon KIM, Kyu Seok OH, Chul Ho YU