Patents by Inventor Guk-Hwan AN
Guk-Hwan AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047214Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Patent number: 11830740Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: GrantFiled: April 19, 2021Date of Patent: November 28, 2023Assignee: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan Kim
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Publication number: 20230006039Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Publication number: 20230005748Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: ApplicationFiled: September 9, 2022Publication date: January 5, 2023Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Publication number: 20220328619Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.Type: ApplicationFiled: June 20, 2022Publication date: October 13, 2022Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Patent number: 11430863Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.Type: GrantFiled: July 14, 2020Date of Patent: August 30, 2022Assignee: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan Kim
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Publication number: 20220052156Abstract: A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer.Type: ApplicationFiled: July 15, 2021Publication date: February 17, 2022Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Patent number: 11171222Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.Type: GrantFiled: May 31, 2019Date of Patent: November 9, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan Kim, Jin Yeong Son
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Publication number: 20210313420Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.Type: ApplicationFiled: July 14, 2020Publication date: October 7, 2021Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Publication number: 20210242024Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Patent number: 11018010Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: GrantFiled: August 1, 2019Date of Patent: May 25, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan Kim
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Publication number: 20200312666Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.Type: ApplicationFiled: August 1, 2019Publication date: October 1, 2020Applicant: MagnaChip Semiconductor, Ltd.Inventor: Guk Hwan KIM
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Publication number: 20200251575Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.Type: ApplicationFiled: May 31, 2019Publication date: August 6, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Guk Hwan KIM, Jin Yeong SON
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Patent number: 10727300Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.Type: GrantFiled: January 12, 2018Date of Patent: July 28, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan Kim, Jin Yeong Son
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Patent number: 10428458Abstract: The present invention relates to a medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers as prepared by the paper making process, a preparation method thereof, and an adhesion prevention barrier using the same. The present invention provides a single phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, to induce capillary action of micropores formed between the fibers and thereby control the gelation time, and provides a composite nonwoven fabric formed by laminating a nonwoven fabric layer comprising a different kind of biodegradable polymer material not susceptible to gelation on the single-phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, thereby improving dimensional stability and convenience of surgical procedure. The present invention further provides a dyed medical nonwoven fabric to improve visibility, allowing easiness of recognizing the placement or location of the medical nonwoven fabric.Type: GrantFiled: February 5, 2016Date of Patent: October 1, 2019Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGYInventors: Jung Nam Im, Dae Young Lim, Guk-Hwan An, Yoon Jin Kim
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Publication number: 20190019866Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.Type: ApplicationFiled: January 12, 2018Publication date: January 17, 2019Applicant: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan KIM, Jin Yeong SON
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Publication number: 20160153143Abstract: The present invention relates to a medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers as prepared by the paper making process, a preparation method thereof, and an adhesion prevention barrier using the same. The present invention provides a single phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, to induce capillary action of micropores formed between the fibers and thereby control the gelation time, and provides a composite nonwoven fabric formed by laminating a nonwoven fabric layer comprising a different kind of biodegradable polymer material not susceptible to gelation on the single-phase of medical nonwoven fabric comprising gelable cellulose derivative short-cut fibers, thereby improving dimensional stability and convenience of surgical procedure. The present invention further provides a dyed medical nonwoven fabric to improve visibility, allowing easiness of recognizing the placement or location of the medical nonwoven fabric.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventors: Jung Nam Im, Dae Young Lim, Guk-Hwan An, Yoon Jin Kim
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Publication number: 20150234799Abstract: An apparatus and method of operating a text related function are provided. The apparatus includes receiving a selection of at least one text region from displayed text, determining at least one classification for one of the at least one text region and the character information based on a connection relationship between at least one piece of character information included in the at least one text region selected, and processing a text related function associated with the at least one piece of character information according to the determined at least one classification.Type: ApplicationFiled: January 28, 2015Publication date: August 20, 2015Inventors: Guk Hwan CHO, Ki Chul SONG, Ji Woo LEE, In Soon KIM, Kyu Seok OH, Chul Ho YU
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Patent number: 8835073Abstract: Disclosed is a polymer membrane for a battery including a porous support including a fiber including a core including a high melting-point polymer; and a sheath including a low melting-point polymer surrounding the core, and a method of preparing the same. The polymer membrane for a battery may further include a proton conductive polymer.Type: GrantFiled: October 7, 2010Date of Patent: September 16, 2014Assignees: Samsung SDI Co., Ltd., Korea Institute of Industrial TechnologyInventors: Sang-Il Han, Hee-Tak Kim, Dae-Young Lim, Jung-Nam Im, Guk-Hwan An, Ki-Young Kim
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Patent number: 8643859Abstract: An image forming apparatus and a control method thereof which performs an auto-recovery function, the image forming apparatus including: a housing including a door; an image forming unit mounted in the housing to form an image on a print medium; a medium discharger which discharges the print medium to an outside of the housing; a finisher mounted on the housing to perform a finishing operation; a discharging direction changer which changes a discharging direction of the print medium to guide the print medium to one of the medium discharger and the finisher; and a controller which controls the image forming unit, the finisher and the discharging direction changer, and selectively performs an auto-recovery operation to automatically recover a jam of the print medium depending upon an occurrence location of the jam of the print medium if the jam occurs from a predetermined location of a print medium feeding path.Type: GrantFiled: April 7, 2011Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-soo Song, Suk-goo Kim, Guk-hwan Lee