Patents by Inventor Gulzar Ahmed Kathawala
Gulzar Ahmed Kathawala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10552259Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.Type: GrantFiled: March 15, 2018Date of Patent: February 4, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Adam Noah Jacobvitz, Gulzar Ahmed Kathawala, Kroum Stanimirov Stoev, Bin Wu
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Publication number: 20190286516Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform addition NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Adam Noah Jacobvitz, Gulzar Ahmed Kathawala, Kroum Stanimirov Stoev, Bin Wu
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Publication number: 20170148525Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive verify voltage adjustment in memory devices. The method includes: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determining a plurality of error parameters, (2) determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determining whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjusting a verify voltage in accordance with the verify adjustment signal, and (5) performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.Type: ApplicationFiled: June 17, 2016Publication date: May 25, 2017Inventors: Gulzar Ahmed Kathawala, Yuan Zhang, Wenzhou Chen, Sheunghee Park
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Patent number: 7952938Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: GrantFiled: May 4, 2010Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Patent number: 7944746Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.Type: GrantFiled: November 27, 2007Date of Patent: May 17, 2011Assignee: Spansion LLCInventors: Gwyn Robert Jones, Mark W Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee
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Publication number: 20100208527Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: ApplicationFiled: May 4, 2010Publication date: August 19, 2010Applicant: SPANSION LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Patent number: 7746698Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.Type: GrantFiled: December 13, 2007Date of Patent: June 29, 2010Assignee: Spansion LLCInventors: Zhizheng Liu, An Chen, Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Gulzar Ahmed Kathawala, Ashot Melik-Martirosian
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Patent number: 7746705Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: GrantFiled: December 10, 2007Date of Patent: June 29, 2010Assignee: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Publication number: 20090154246Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Zhizheng Liu, An Chen, Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Gulzar Ahmed Kathawala, Ashot Melik-Martirosian
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Publication number: 20090147589Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: Spansion LLCInventors: Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate, Kuo-Tung Chang, Sheung-Hee Park, Gabrielle Wing Han Leung
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Publication number: 20090135659Abstract: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles.Type: ApplicationFiled: November 27, 2007Publication date: May 28, 2009Applicant: SPANSION LLCInventors: Gwyn Robert Jones, Mark W. Randolph, John Darilek, Sean O'Mullan, Jacob Marcantel, Rick Anundson, Adam Shackleton, Xiaojian Chu, Abhijit Raghunathan, Asif Arfi, Gulzar Ahmed Kathawala, Zhizheng Liu, Sung-Chul Lee