Patents by Inventor Gun-Ok Jung
Gun-Ok Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9537470Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: August 12, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Patent number: 9318607Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.Type: GrantFiled: May 9, 2014Date of Patent: April 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Woo Seo, Gun-Ok Jung, Min-Su Kim, Sang-Shin Han, Ju-Hyun Kang, Uk-Rae Cho
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Publication number: 20150349756Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
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Patent number: 9158354Abstract: A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.Type: GrantFiled: March 12, 2013Date of Patent: October 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ken Keon Shin, Hoi Jin Lee, Gun Ok Jung, Min Su Kim
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Patent number: 9130550Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: June 4, 2014Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Publication number: 20150014775Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.Type: ApplicationFiled: May 9, 2014Publication date: January 15, 2015Inventors: Jae-Woo SEO, Gun-Ok JUNG, Min-Su KIM, Sang-Shin HAN, Ju-Hyun KANG, Uk-Rae CHO
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Publication number: 20140368246Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: June 4, 2014Publication date: December 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
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Patent number: 8810279Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.Type: GrantFiled: December 28, 2012Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ken Keon Shim, Hoi Jin Lee, Gun Ok Jung
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Patent number: 8542033Abstract: A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.Type: GrantFiled: September 16, 2011Date of Patent: September 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoung-Wook Lee, Gun-Ok Jung, Suhwan Kim, Ah-Reum Kim, Rahul Singh
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Publication number: 20130246834Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.Type: ApplicationFiled: December 28, 2012Publication date: September 19, 2013Inventors: Ken Keon Shim, Hoi Jin Lee, Gun Ok Jung
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Publication number: 20130246819Abstract: A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Inventors: Ken Keon Shin, Hoi Jin Lee, Gun Ok Jung, Min Su Kim
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Patent number: 8531208Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.Type: GrantFiled: March 2, 2012Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ok Jung, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
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Publication number: 20130194019Abstract: The semiconductor integrated circuit includes a clock tree that transmits a clock signal to a plurality of tree branches, a plurality of pulse generators, and a plurality of pulse distribution networks. Each pulse generator generates a pulse in response to the clock signal transmitted through the tree branches. Each pulse distribution network is in communication with a pulse generator of the plurality of pulse generators, and is constructed and arranged to transmit the pulse generated by each pulse generator to a plurality of pulse sinks.Type: ApplicationFiled: September 13, 2012Publication date: August 1, 2013Inventors: Hoi Jin Lee, Gun Ok Jung
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Publication number: 20120223739Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Inventors: Gun Ok JUNG, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
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Publication number: 20120139584Abstract: A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.Type: ApplicationFiled: September 16, 2011Publication date: June 7, 2012Applicants: SEOUL NATIONAL UNIVERSITY R&D FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyoung-Wook Lee, Gun-Ok Jung, Suhwan Kim, Ah-Reum Kim, Rahul Singh
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Patent number: 7971088Abstract: A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.Type: GrantFiled: February 25, 2008Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Gun-Ok Jung, Chung-Hee Kim
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Patent number: 7944267Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.Type: GrantFiled: April 1, 2010Date of Patent: May 17, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Gun-Ok Jung
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Patent number: 7893718Abstract: High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.Type: GrantFiled: August 13, 2009Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Bae Park, Gun Ok Jung, Young Min Shin, Hoi Jin Lee, Chang Jun Choi, Min Su Kim
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Publication number: 20100188121Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Inventor: GUN-OK JUNG
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Patent number: 7705656Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.Type: GrantFiled: July 5, 2006Date of Patent: April 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Gun-Ok Jung