Patents by Inventor Gunjan Pandya

Gunjan Pandya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Negative bitline write assist circuit and method for operating the same
    Patent number: 10902893
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • Negative bitline write assist circuit and method for operating the same
    Patent number: 10818326
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME
    Publication number: 20180226109
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Application
    Filed: December 26, 2017
    Publication date: August 9, 2018
    Applicant: Intel Corporation
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME
    Publication number: 20180082722
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Application
    Filed: November 10, 2017
    Publication date: March 22, 2018
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • Negative bitline write assist circuit and method for operating the same
    Patent number: 9818460
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME
    Publication number: 20160267952
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • Negative bitline write assist circuit and method for operating the same
    Patent number: 9378788
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: June 28, 2016
    Assignee: INTEL CORPORATION
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME
    Publication number: 20140169106
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Application
    Filed: March 15, 2012
    Publication date: June 19, 2014
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • Hierarchical DRAM sensing
    Patent number: 8406073
    Abstract: A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Gunjan Pandya, Kevin Zhang, Fatih Hamzaoglu, Balaji Srinivasan, Swaroop Ghosh, Meterelliyoz Mesut
  • Memory circuit
    Publication number: 20060114711
    Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan Pandya, Vivek De
  • SRAM WITH FORWARD BODY BIASING TO IMPROVE READ CELL STABILITY
    Publication number: 20050213370
    Abstract: A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 29, 2005
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Ali Farhang, Gunjan Pandya, Vivek De