Abstract: An apparatus for function testing of electronic circuits includes a tester array having a terminal. A test circuit has at least two resistor elements, a common circuit node connected to the resistor elements for connection to the terminal of the tester array, and terminals of the resistor elements each being remote from the circuit node for connection to a respective output of an electronic circuit to be tested. A testing method for function testing of electronic circuits with such an apparatus includes placing the electronic circuit into a state in which signals are present at an output of the electronic circuit to be tested. The electronic circuit is function tested with respect to a resultant signal being established at the common circuit node.

Abstract: A method of operating a semiconductor memory with a facility for performing integrated parallel testing, wherein the semiconductor memory is subdivided into n identical cell fields with addressable storage cells, each of the storage cells of each of the cell fields being addressable within a storage cycle simultaneously with, respectively, one storage cell of each of the other cell fields, wherein during a testing operation of the semiconductor memory, the storage cell of one of the n cell fields addressed for the purpose of reading out (read cycle) of a stored test datum has, due to a writing-in process, the same stored test datum as each of the other addressed storage cells addressed in the same read cycle in the case ("go" case) wherein the semiconductor memory is in order, which comprises, within the semiconductor memory, in the testing operation, simultaneously comparing within a read cycle, the test data read out from each of the storage cells addressed within the read cycle of the respective n cell fie