Patents by Inventor Guo Hua Zhong

Guo Hua Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layout and pad floor plan of power transistor for good performance of SPU and STOG
    Patent number: 8691684
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 8, 2014
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Guo Hua Zhong, Mei Yang
  • LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG
    Publication number: 20130267087
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 10, 2013
    Inventors: Guo Hua Zhong, Mei Yang
  • Layout and pad floor plan of power transistor for good performance of SPU and STOG
    Patent number: 8471299
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: Guo Hua Zhong, Mei Yang
  • LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG
    Publication number: 20110074511
    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
    Type: Application
    Filed: August 23, 2010
    Publication date: March 31, 2011
    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.
    Inventors: Guo Hua Zhong, Mei Yang