Abstract: The present invention is directed to a compound represented by the following structural formula or a pharmaceutically acceptable salt thereof. Pharmaceutical compositions and method of use of the compounds are also described.

Abstract: A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.

Abstract: A high-speed latch circuit includes a latching unit for latching an inputted signal, a signal input unit connected to the latching unit and a clock control unit connected to the signal input unit. The clock control unit includes a first switch element, a second switch element connected to the first switch element and an inverter connected to the second switch element. The first switch element and the inverter are both connected to a clock signal input end. The high-speed latch circuit of the present invention has a simple circuit structure, shortens the triggering time of the signal and reduces chances of wrong triggering.

Abstract: An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.

Abstract: A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.

Abstract: A spread spectrum generating circuit comprises an external PLL and an internal PLL. The external PLL comprises a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider, each of them connecting successively. The frequency divider is connected to the phase detector in order to form an external loop. The internal PLL comprises the phase detector, the low-pass filter and the voltage-controlled oscillator of the external PLL, each of them connecting successively. An output terminal of the voltage-controlled oscillator connects with a counter, and the output terminal of the counter connects to an input of the oscillator in order to form an internal loop. The present invention is compatible with the conventional ones, and has lower design risk and higher circuit reliability; compared with the general circuit, it has drastically reduced the area and power consumption, which allows more flexible design and meets more demands.

Abstract: The present invention relates to compounds represented by Structural Formula (I) or a pharmaceutically acceptable salt thereof. Definitions for the variables are provided herein.

Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

Abstract: An equalization system includes an adjustable equalization unit, a common-mode feedback unit connected with the equalization unit, a current balance driving unit connected with the feedback and equalization units, a first high-pass filter unit connected with the equalization unit, a second high-pass filter unit connected with the driving unit, a first low-pass filter unit connected with the equalization unit, a second low-pass filter unit connected with the driving unit, a first energy detection unit connected with two high-pass filter units, a second energy detection unit connected with two low-pass filter units, a first analog-to-digital converter unit connected with the first energy detection unit, a second analog-to-digital converter unit connected with the second energy detection unit and a state decision unit connected with two analog-to-digital converter units outputs a control signal for adjusting the equalization unit.

Abstract: A duty cycle adjusting system includes a detection circuit, a first clock signal adjusting circuit connected with the detection circuit, and a second clock signal adjusting circuit connected with the detection circuit, wherein the detection circuit detects a duty cycle of a first output signal outputted by the first clock signal adjusting circuit and a duty cycle of a second output signal outputted by the second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, the first and second output signals are a pair of differential clock signals, the first and second detection signals are adapted for respectively adjusting rising edges of the pair of differential clock signals. No peripheral circuit is needed to provide the bias in the duty cycle adjusting system. The duty cycle adjusting system has the simple structure and can be independently applied to the clock path.

Abstract: A duty cycle correction method includes detecting independently a relative delay time of two input differential signals; equating the sum of two relative delay time with the cycle of the input differential signals; and adjusting the two delay time to the same value. A corresponding implementation circuit includes two time delay units; two relative phase detectors connecting simultaneously with each of the two time delay units; a charge pump connecting with the output of each of the two relative phase detectors, with its output connecting to the two time delay units in order to form a loop; and a synthesis output unit connecting with both the time delay units, thereby generating output signals. The adjusting range of duty cycle becomes much wider. The implementation circuit is absolutely symmetrical, so a duty cycle with high accuracy can be obtain.

Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

Abstract: A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyses sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided.

Abstract: A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.

Abstract: A high-speed latch circuit includes a latching unit for latching an inputted signal, a signal input unit connected to the latching unit and a clock control unit connected to the signal input unit. The clock control unit includes a first switch element, a second switch element connected to the first switch element and an inverter connected to the second switch element. The first switch element and the inverter are both connected to a clock signal input end. The high-speed latch circuit of the present invention has a simple circuit structure, shortens the triggering time of the signal and reduces chances of wrong triggering.

Abstract: A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit.

Abstract: A frequency multiplier system, for outputting a single phase clock of N multiplied frequency after processing an inputted clock, N?2, includes a frequency divider receiving the inputted clock, an interpolator connected with the frequency divider, a phase equalizer connected with the interpolator, and a combinational logic circuit connected with the phase equalizer, wherein the frequency divider outputs an orthogonal clock having a two-phases frequency that is a half of the inputted clock to the interpolator, the interpolator outputs a 2N-phases clock to the phase equalizer, the phase equalizer homogenizes a phase skew of the 2N-phases clock, the combinational logic circuit synthesizes the homogenized 2N-phases clock into a single phase clock of N multiplied frequency. And a method of multiplying frequency is provided. The present invention does not need feedback circuits, and therefore is stable and fast-speed , saves area, and reduces energy consumption.

Abstract: An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: An equalization system includes an adjustable equalization unit, a common-mode feedback unit connected with the equalization unit, a current balance driving unit connected with the feedback and equalization units, a first high-pass filter unit connected with the equalization unit, a second high-pass filter unit connected with the driving unit, a first low-pass filter unit connected with the equalization unit, a second low-pass filter unit connected with the driving unit, a first energy detection unit connected with two high-pass filter units, a second energy detection unit connected with two low-pass filter units, a first analog-to-digital converter unit connected with the first energy detection unit, a second analog-to-digital converter unit connected with the second energy detection unit and a state decision unit connected with two analog-to-digital converter units outputs a control signal for adjusting the equalization unit.