Patents by Inventor Guotao Wang

Guotao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135516
    Abstract: Systems and methods for motion correction in medical imaging are provided in the present disclosure. The systems may obtain at least two image sequences relating to a subject. Each of the at least two image sequences may be reconstructed based on image data that is acquired by a medical imaging device during one of at least two time periods. The subject may undergo a physiological motion during the at least two time periods. The systems may generate, based on the at least two image sequences, at least one corrected image sequence relating to the subject by correcting, using a motion correction model, an artifact caused by the physiological motion.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 25, 2024
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Guotao QUAN, Yi WANG, Jiao TIAN
  • Publication number: 20240128256
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J. DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG
  • Publication number: 20240123049
    Abstract: Provided is a new-type cis-replicon construct for efficiently expressing a target protein, which comprises an RNA polymerase coding unit and a target protein coding unit. The replicon construct can drive the replication of the target protein coding unit and reduce or avoid the replication and expression of the RNA polymerase, thereby effectively improving the expression of the target protein and reducing the expression of the non-target protein.
    Type: Application
    Filed: February 7, 2022
    Publication date: April 18, 2024
    Applicant: ZHENGZHOU UNIVERSITY
    Inventors: Shoutao ZHANG, Qiang MA, Qingnan TIAN, Tian WANG, Yonghui HUANG, Guotao LIU, Zhen TIAN
  • Patent number: 11817444
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Robert L Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20220231007
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J. DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG
  • Patent number: 11373966
    Abstract: A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Tae Hong Kim, Jiangqi He, Guotao Wang
  • Publication number: 20220189889
    Abstract: A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.
    Type: Application
    Filed: September 2, 2020
    Publication date: June 16, 2022
    Inventors: Tae Hong Kim, Jiangqi He, Guotao Wang
  • Patent number: 11348911
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20220157803
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Robert L. SANKMAN, Sairam AGRAHARAM, Shengquan OU, Thomas J DE BONIS, Todd SPENCER, Yang SUN, Guotao WANG
  • Publication number: 20210391281
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 16, 2021
    Applicant: INTEL CORPORATION
    Inventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
  • Patent number: 11114388
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
  • Publication number: 20200402934
    Abstract: A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Tae Hong Kim, Jiangqi He, Guotao Wang
  • Publication number: 20200395352
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 17, 2020
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J. De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Patent number: 10700051
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20190371778
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J. De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Publication number: 20190259713
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Applicant: INTEL CORPORATION
    Inventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
  • Patent number: 10256198
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
  • Publication number: 20180277492
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Applicant: INTEL CORPORATION
    Inventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
  • Patent number: 9594617
    Abstract: Disclosed are a method and an apparatus for positioning crash, for solving the problem of the prior art that the positioning of the cause of the crash cannot be ensured. The method includes: setting monitoring points in a terminal and a test target in advance; monitoring the operation of the test target, and when the test target crashes, acquiring parameters of the monitoring points and parameter values thereof to generate a mirror file, the parameters of the monitoring points including the parameters of the monitoring points in the test target and in the terminal; acquiring the mirror file and viewing the parameters of the monitoring points in the mirror file and the parameter values thereof; analyzing the parameters of the monitoring points and the parameter values thereof and positioning the cause of the crash of the test target.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 14, 2017
    Assignee: BEIJING QIHOO TECHNOLOGY COMPANY LIMITED
    Inventors: Guotao Wang, Qingping Liu
  • Publication number: 20150317232
    Abstract: Disclosed are a method and an apparatus for positioning crash, for solving the problem of the prior art that the positioning of the cause of the crash cannot be ensured. The method includes: setting monitoring points in a terminal and a test target in advance; monitoring the operation of the test target, and when the test target crashes, acquiring parameters of the monitoring points and parameter values thereof to generate a mirror file, the parameters of the monitoring points including the parameters of the monitoring points in the test target and in the terminal; acquiring the mirror file and viewing the parameters of the monitoring points in the mirror file and the parameter values thereof; analyzing the parameters of the monitoring points and the parameter values thereof and positioning the cause of the crash of the test target.
    Type: Application
    Filed: September 27, 2013
    Publication date: November 5, 2015
    Applicant: Qizhi Software (Beijing) Company Limited
    Inventors: Guotao WANG, Qingping LIU