Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

Abstract: Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.

Abstract: Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

Abstract: One IC product disclosed herein includes, among other things, a semiconductor substrate, a first anti-fuse device formed on the semiconductor substrate, the first anti-fuse device comprising at least one first fin formed with a first fin pitch, a first source region and a first drain region, wherein the first anti-fuse device is adapted to breakdown when a first programing voltage is applied to the first anti-fuse device, and a second anti-fuse device formed on the semiconductor substrate, the second anti-fuse device comprising at least one second fin formed with a second fin pitch, a second source region and a second drain region, wherein the second anti-fuse device is adapted to breakdown when a second programing voltage is applied to the second anti-fuse device, wherein the first fin pitch is greater than the second fin pitch and wherein the first programming voltage is greater than the second programing voltage.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

Abstract: One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.