Abstract: The embodiments of the present application provide a display panel and a display apparatus. The display panel includes a plurality of light-emitting elements including a first-color light-emitting element and a second-color light-emitting element; a plurality of conductive parts electrically connected to the light-emitting elements, wherein in the plurality of conductive parts, a conductive part electrically connected to the first-color light-emitting element is a first conductive part, and a conductive part electrically connected to the second-color light-emitting element is a second conductive part; and a first scan signal line overlapped with and insulated from the conductive parts, wherein an overlapping area of the first scan signal line and the first conductive part is larger than an overlapping area of the first scan signal line and the second conductive part.

Abstract: Provided are a display panel and a display device. The display panel includes a display region, a non-display region bordering two sides of the display region at least in a first direction and a hole-digging region. The distance from the hole-digging region to the non-display region on a first side of the display region is smaller than the distance from the hole-digging region to the non-display region on a second side of the display region. The display region includes pixel circuits and initialization signal lines. The non-display region includes cascaded initialization signal shift register units. The initialization signal shift register unit includes a first initialization signal shift register unit located in the non-display region on the first side of the display region. The first initialization signal shift register unit is electrically connected to a corresponding initialization signal line having a partial line segment extending around the hole-digging region.

Abstract: The present application discloses a display panel, an integrated chip and a display apparatus. The display panel includes: a first display area and a second display area; and pixel circuits including first pixel circuits and second pixel circuits, wherein the first pixel circuits are configured to provide driving currents to light emitting elements of the first display area, and the second pixel circuits are configured to provide driving currents to light emitting elements of the second display area, the pixel circuits receive a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, the first pixel circuits receive the first bias adjustment signal, and the second pixel circuits receive the second bias adjustment signals, a voltage value of the first bias adjustment signal is V1, and a voltage value of the second bias adjustment signal is V2, wherein V1?V2.

Abstract: Provided are a display panel and a display device. The display panel includes a first display region, a second display region and pixel circuits. The pixel circuits include a first pixel circuit and a second pixel circuit. The first pixel circuit is configured to provide a drive current for a light-emitting element in the first display region. The second pixel circuit is configured to provide a drive current for a light-emitting element in the second display region. The pixel circuits further include at least one bias adjustment module, each of which is configured to provide a bias adjustment signal for a respective one drive transistor. A preset electrode of a drive transistor in the first pixel circuit is connected to one bias adjustment module and a preset electrode of a drive transistor in the second pixel circuit is connected to no bias adjustment module.

Abstract: Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a first function region. The second display region includes a first signal line extending in the second direction and including a first segment and a second segment that are separated by the first function region. The first display region includes a first display sub-region. The first display sub-region includes a third signal line extending in the second direction and electrically connected to the first segment and the second segment. In the same pixel circuit of the first display sub-region, the second signal line and the third signal line are located on the same side of a fourth signal line.

Abstract: Provided are a display panel and a display device. The display panel includes a display region, a non-display region bordering two sides of the display region at least in a first direction and a hole-digging region. The distance from the hole-digging region to the non-display region on a first side of the display region is smaller than the distance from the hole-digging region to the non-display region on a second side of the display region. The display region includes pixel circuits and initialization signal lines. The non-display region includes cascaded initialization signal shift register units. The initialization signal shift register unit includes a first initialization signal shift register unit located in the non-display region on the first side of the display region. The first initialization signal shift register unit is electrically connected to a corresponding initialization signal line having a partial line segment extending around the hole-digging region.

Abstract: Provided are a display panel and a display device. The display panel includes a display region, a non-display region at least partially surrounding the display region, and a fan-out region. The display region includes a plurality of scanning lines extending along a first direction and a plurality of data lines extending along a second direction, where the first direction intersects with the second direction. The non-display region includes a plurality of pads. The fan-out region is configured on one side of the display region closer to the plurality of pads, where at least part of the fan-out region is disposed in the display region. The fan-out region is provided with a plurality of fan-out wires for connecting the plurality of data lines to the corresponding pads.

Abstract: The present disclosure provides a method for cleaning a bonding interface before bonding. The method includes: providing a first surface and a second surface for bonding, the first surface being a non-crystal surface and the second surface being a crystal surface; and cleaning the first surface and the second surface with ammonia respectively before bonding, wherein at least one of parameters of an ammonia concentration and a cleaning temperature for cleaning the first surface is higher than a counterpart of parameters for cleaning the second surface.

Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Abstract: The present disclosure provides a method for cleaning a bonding interface before bonding. The method includes: providing a first surface and a second surface for bonding, the first surface being a non-crystal surface and the second surface being a crystal surface; and cleaning the first surface and the second surface with ammonia respectively before bonding, wherein at least one of parameters of an ammonia concentration and a cleaning temperature for cleaning the first surface is higher than a counterpart of parameters for cleaning the second surface.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: injecting bubbling ions into the semiconductor substrate to form a splitting layer, and injecting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are injected, and causing the semiconductor substrate to split at the position of the splitting layer; thinning a splitting surface of the split semiconductor substrate; and performing a second heat treatment for the thinned semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are injected.

Abstract: Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface. A second insulating layer is disposed on the second surface. The second substrate includes a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer; and forming a passivation layer on a surface of the second insulating layer by means of adhesion, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.

Abstract: A method is provided for preparing a semiconductor substrate with smooth edges. The method includes: providing a first substrate and a second substrate; forming an insulating layer on a surface of the first substrate and/or the second substrate; bonding the first substrate and the second substrate by using the insulating layer as an intermediate layer; conducting a chamfering process on the bonded first substrate and insulating layer; and conducting edge polishing on the first substrate and insulating layer subjected to the chamfering process.

Abstract: Disclosed are a low-warpage semiconductor substrate and a method for preparing the same. The method includes: providing a first substrate and a second substrate, the first substrate comprising a first surface and a second surface which are opposite to each other, the first surface being provided with a first insulating layer. A second insulating layer is dispose on the second surface. A support layer is disposed on the second substrate. An oxidation layer is arranged on a surface of the support layer and a device layer is arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate; and forming a passivation layer on a surface of the second insulating layer by epitaxy, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.

Abstract: Disclosed herein is a microwave heating device. A material conduit runs into and out of a microwave irradiation cavity through a cavity wall of the microwave irradiation cavity. A waveguide tube for guiding microwave is installed on the cavity wall. A heat exchange tube is disposed inside the material conduit and enters and leaves the material conduit from the nozzle or wall of the material conduit. The microwave heating device is used in chemical reactions. The microwave heating device may control the temperature of the material inside the material conduit under continuous irradiation of microwave.