Abstract: The present invention discloses a negative charge pump feedback circuit, wherein the feedback circuit is connected between an AND gate and the output terminal of the negative charge pump, and a clock signal is connected to the negative charge pump through the AND gate and under the control of the feedback signal, with the feedback circuit including a switch-capacitor circuit and a comparator; a first terminal of a first capacitor of the switch-capacitor circuit is connected to the output terminal of the negative charge pump through a first switch, and grounded through a second switch; a first terminal of a second capacitor is connected to a second terminal of the first capacitor, grounded though a third switch, and connected to the comparator though a fourth switch; an adjustable capacitor is connected in parallel to both terminals of the second capacitor; a positive-phase input terminal of the comparator is connected to a reference voltage.

Abstract: An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.

Abstract: An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.

Abstract: The present invention discloses a negative charge pump feedback circuit, wherein the feedback circuit is connected between an AND gate and the output terminal of the negative charge pump, and a clock signal is connected to the negative charge pump through the AND gate and under the control of the feedback signal, with the feedback circuit including a switch-capacitor circuit and a comparator; a first terminal of a first capacitor of the switch-capacitor circuit is connected to the output terminal of the negative charge pump through a first switch, and grounded through a second switch; a first terminal of a second capacitor is connected to a second terminal of the first capacitor, grounded though a third switch, and connected to the comparator though a fourth switch; an adjustable capacitor is connected in parallel to both terminals of the second capacitor; a positive-phase input terminal of the comparator is connected to a reference voltage.

Abstract: A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage.

Abstract: A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage.

Abstract: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit.

Abstract: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit.