Patents by Inventor Gurjeet S. Bains

Gurjeet S. Bains has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reducing defects in a semiconductor lithographic process
    Patent number: 6222936
    Abstract: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Gurjeet S. Bains, David A. Steele, Jonathan A. Orth, Ramkumar Subramanian
  • Method for reducing defects in a semiconductor lithographic process
    Patent number: 5985497
    Abstract: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khoi A. Phan, Gurjeet S. Bains, David A. Steele, Jonathan A. Orth, Ramkumar Subramanian