Abstract: Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

Abstract: A signal generator is disclosed that in one form employs an indirect digital-to-analog converter (DAC) assisted frequency synthesizer for switching a steering current into or out of a phase locked loop (PLL) filter capacitor. The signal generator provides fast switching performance and loop bandwidth adjustment to reduce phase noise and improve phase jitter performance. The signal generator comprises a channel signal selector, a digital-to-analog converter, a window generator circuit, a window comparator, a steering current circuit, a PLL circuit with voltage controlled oscillator (VCO), programmable divider, and a reference oscillator.